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-rw-r--r--tests/arch/xilinx/memory_params.ys4
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/arch/xilinx/memory_params.ys b/tests/arch/xilinx/memory_params.ys
index 657629e0f..c1b0ca489 100644
--- a/tests/arch/xilinx/memory_params.ys
+++ b/tests/arch/xilinx/memory_params.ys
@@ -37,10 +37,10 @@ cd sync_ram_sdp
select -assert-count 0 t:RAMB18E1
select -assert-count 4 t:RAM128X1D
-# More than 18K bits and addr <= 36: -> RAMB36E1
+# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1
design -reset
read_verilog ../common/memory_params.v
-chparam -set ADDRESS_WIDTH 15 -set DATA_WIDTH 1 sync_ram_sdp
+chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp
synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp
select -assert-count 1 t:RAMB36E1