diff options
Diffstat (limited to 'tests/arch/xilinx/logic.ys')
| -rw-r--r-- | tests/arch/xilinx/logic.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/arch/xilinx/logic.ys b/tests/arch/xilinx/logic.ys index d5b5c1a37..61a9314cc 100644 --- a/tests/arch/xilinx/logic.ys +++ b/tests/arch/xilinx/logic.ys @@ -1,7 +1,7 @@ read_verilog ../common/logic.v hierarchy -top top proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module |