1 files changed, 28 insertions, 0 deletions
diff --git a/tests/arch/nexus/mul.ys b/tests/arch/nexus/mul.ys
new file mode 100644
index 000000000..27ea3e04e
--- /dev/null
+++ b/tests/arch/nexus/mul.ys
@@ -0,0 +1,28 @@
+read_verilog ../common/mul.v
+hierarchy -top top
+proc
+
+design -save read
+
+equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 7 t:CCU2
+select -assert-max 5 t:WIDEFN9
+select -assert-max 62 t:LUT4
+
+select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:CCU2 t:WIDEFN9 %% t:* %D
+
+design -load read
+
+equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus -abc9
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+stat
+
+select -assert-count 7 t:CCU2
+select -assert-max 12 t:WIDEFN9
+select -assert-max 58 t:LUT4
+
+select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:CCU2 t:WIDEFN9 %% t:* %D