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-rw-r--r--tests/arch/intel_alm/add_sub.ys4
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/arch/intel_alm/add_sub.ys b/tests/arch/intel_alm/add_sub.ys
index 2d464788b..8f87adf27 100644
--- a/tests/arch/intel_alm/add_sub.ys
+++ b/tests/arch/intel_alm/add_sub.ys
@@ -4,7 +4,7 @@ equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cycl
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
-select -assert-count 8 t:MISTRAL_ALUT_ARITH
+select -assert-count 9 t:MISTRAL_ALUT_ARITH
select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
design -reset
@@ -14,5 +14,5 @@ equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cycl
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
-select -assert-count 8 t:MISTRAL_ALUT_ARITH
+select -assert-count 9 t:MISTRAL_ALUT_ARITH
select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D