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Diffstat (limited to 'tests/arch/ice40/rom.ys')
| -rw-r--r-- | tests/arch/ice40/rom.ys | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/tests/arch/ice40/rom.ys b/tests/arch/ice40/rom.ys new file mode 100644 index 000000000..41d214e2a --- /dev/null +++ b/tests/arch/ice40/rom.ys @@ -0,0 +1,8 @@ +read_verilog rom.v +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 5 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D |