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-rw-r--r--tests/arch/ice40/counter.ys2
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/arch/ice40/counter.ys b/tests/arch/ice40/counter.ys
index f112eb97d..7bbc4f2c3 100644
--- a/tests/arch/ice40/counter.ys
+++ b/tests/arch/ice40/counter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/counter.v
hierarchy -top top
proc
flatten
-equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 6 t:SB_CARRY