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-rw-r--r--tests/arch/ecp5/bug1459.ys25
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diff --git a/tests/arch/ecp5/bug1459.ys b/tests/arch/ecp5/bug1459.ys
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+++ b/tests/arch/ecp5/bug1459.ys
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+read_verilog <<EOT
+module register_file(
+ input wire clk,
+ input wire write_enable,
+ input wire [63:0] write_data,
+ input wire [4:0] write_reg,
+ input wire [4:0] read1_reg,
+ output reg [63:0] read1_data,
+ );
+
+ reg [63:0] registers[0:31];
+
+ always @(posedge clk) begin
+ if (write_enable == 1'b1) begin
+ registers[write_reg] <= write_data;
+ end
+ end
+
+ always @(all) begin
+ read1_data <= registers[read1_reg];
+ end
+endmodule
+EOT
+
+synth_ecp5 -abc9