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Diffstat (limited to 'tests/arch/anlogic/add_sub.ys')
| -rw-r--r-- | tests/arch/anlogic/add_sub.ys | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/tests/arch/anlogic/add_sub.ys b/tests/arch/anlogic/add_sub.ys new file mode 100644 index 000000000..5396ce7ec --- /dev/null +++ b/tests/arch/anlogic/add_sub.ys @@ -0,0 +1,10 @@ +read_verilog ../common/add_sub.v +hierarchy -top top +proc +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:AL_MAP_ADDER +select -assert-count 4 t:AL_MAP_LUT1 + +select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D |