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-rw-r--r--tests/anlogic/memory.v21
1 files changed, 21 insertions, 0 deletions
diff --git a/tests/anlogic/memory.v b/tests/anlogic/memory.v
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+++ b/tests/anlogic/memory.v
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+module top
+(
+ input [7:0] data_a,
+ input [6:1] addr_a,
+ input we_a, clk,
+ output reg [7:0] q_a
+);
+ // Declare the RAM variable
+ reg [7:0] ram[63:0];
+
+ // Port A
+ always @ (posedge clk)
+ begin
+ if (we_a)
+ begin
+ ram[addr_a] <= data_a;
+ q_a <= data_a;
+ end
+ q_a <= ram[addr_a];
+ end
+endmodule