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+read_verilog latches.v
+design -save read
+
+proc
+async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
+flatten
+synth_anlogic
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+
+design -load read
+synth_anlogic
+cd top
+select -assert-count 2 t:AL_MAP_LUT3
+select -assert-count 1 t:AL_MAP_LUT5
+select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT5 %% t:* %D