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-rw-r--r--tests/anlogic/add_sub.v13
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/anlogic/add_sub.v b/tests/anlogic/add_sub.v
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+++ b/tests/anlogic/add_sub.v
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+module top
+(
+ input [3:0] x,
+ input [3:0] y,
+
+ output [3:0] A,
+ output [3:0] B
+ );
+
+assign A = x + y;
+assign B = x - y;
+
+endmodule