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-rw-r--r--techlibs/xilinx/abc9_map.v32
-rw-r--r--techlibs/xilinx/abc9_model.v14
-rw-r--r--techlibs/xilinx/abc9_unmap.v3
-rw-r--r--techlibs/xilinx/abc9_xc7.box26
-rw-r--r--techlibs/xilinx/cells_sim.v16
5 files changed, 55 insertions, 36 deletions
diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index d04cdb5eb..b36d93c5d 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -161,8 +161,10 @@ module FDCE (output Q, input C, CE, D, CLR);
// control is not directly
// supported by abc9 but its
// behaviour is captured by
- // $__ABC9_ASYNC below
+ // $__ABC9_ASYNC1 below
);
+ // Since this is an async flop, async behaviour is dealt with here
+ \$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
end
else begin
assign Q = QQ;
@@ -177,13 +179,12 @@ module FDCE (output Q, input C, CE, D, CLR);
// control is not directly
// supported by abc9 but its
// behaviour is captured by
- // $__ABC9_ASYNC below
+ // $__ABC9_ASYNC0 below
);
+ // Since this is an async flop, async behaviour is dealt with here
+ \$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
end endgenerate
\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
- // Since this is an async flop, async behaviour is also dealt with
- // using the $_ABC9_ASYNC box by abc9_map.v
- \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
// Special signals
wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
@@ -203,8 +204,9 @@ module FDCE_1 (output Q, input C, CE, D, CLR);
// control is not directly
// supported by abc9 but its
// behaviour is captured by
- // $__ABC9_ASYNC below
+ // $__ABC9_ASYNC1 below
);
+ \$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ));
end
else begin
assign Q = QQ;
@@ -216,11 +218,11 @@ module FDCE_1 (output Q, input C, CE, D, CLR);
// control is not directly
// supported by abc9 but its
// behaviour is captured by
- // $__ABC9_ASYNC below
+ // $__ABC9_ASYNC0 below
);
+ \$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ));
end endgenerate
\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
- \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ));
// Special signals
wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
@@ -247,8 +249,9 @@ module FDPE (output Q, input C, CE, D, PRE);
// control is not directly
// supported by abc9 but its
// behaviour is captured by
- // $__ABC9_ASYNC below
+ // $__ABC9_ASYNC0 below
);
+ \$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
end
else begin
assign Q = QQ;
@@ -263,11 +266,11 @@ module FDPE (output Q, input C, CE, D, PRE);
// control is not directly
// supported by abc9 but its
// behaviour is captured by
- // $__ABC9_ASYNC below
+ // $__ABC9_ASYNC1 below
);
+ \$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
end endgenerate
\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
- \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
// Special signals
wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
@@ -287,8 +290,9 @@ module FDPE_1 (output Q, input C, CE, D, PRE);
// control is not directly
// supported by abc9 but its
// behaviour is captured by
- // $__ABC9_ASYNC below
+ // $__ABC9_ASYNC0 below
);
+ \$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ));
end
else begin
assign Q = QQ;
@@ -300,11 +304,11 @@ module FDPE_1 (output Q, input C, CE, D, PRE);
// control is not directly
// supported by abc9 but its
// behaviour is captured by
- // $__ABC9_ASYNC below
+ // $__ABC9_ASYNC1 below
);
+ \$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ));
end endgenerate
\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
- \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ));
// Special signals
wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v
index cc0e5ec41..c793396a4 100644
--- a/techlibs/xilinx/abc9_model.v
+++ b/techlibs/xilinx/abc9_model.v
@@ -33,11 +33,19 @@ endmodule
module \$__ABC9_FF_ (input D, output Q);
endmodule
+// Box to emulate async behaviour of FDC*
(* abc_box_id = 1000 *)
-module \$__ABC9_ASYNC (input A, S, output Y);
+module \$__ABC9_ASYNC0 (input A, S, output Y);
+ assign Y = S ? 1'b0 : A;
endmodule
-// Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
+// Box to emulate async behaviour of FDP*
+(* abc_box_id = 1001 *)
+module \$__ABC9_ASYNC1 (input A, S, output Y);
+ assign Y = S ? 1'b0 : A;
+endmodule
+
+// Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32}
// Necessary since RAMD* and SRL* have both combinatorial (i.e.
// same-cycle read operation) and sequential (write operation
// is only committed on the next clock edge).
@@ -46,7 +54,7 @@ endmodule
(* abc9_box_id=2000 *)
module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
endmodule
-// Box to emulate comb/seq behaviour of RAMD128
+// Box to emulate comb/seq behaviour of RAM128
(* abc9_box_id=2001 *)
module \$__ABC9_LUT7 (input A, input [6:0] S, output Y);
endmodule
diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v
index 21fe78d08..46526007d 100644
--- a/techlibs/xilinx/abc9_unmap.v
+++ b/techlibs/xilinx/abc9_unmap.v
@@ -20,7 +20,8 @@
// ============================================================================
-module \$__ABC9_ASYNC (input A, S, output Y);
+(* techmap_celltype = "$__ABC9_ASYNC0 $__ABC9_ASYNC1" *)
+module \$__ABC9_ASYNC01 (input A, S, output Y);
assign Y = A;
endmodule
diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box
index 4e632c0fa..a2d119284 100644
--- a/techlibs/xilinx/abc9_xc7.box
+++ b/techlibs/xilinx/abc9_xc7.box
@@ -41,10 +41,16 @@ CARRY4 4 1 10 8
592 540 520 356 - 512 548 292 - 228
580 526 507 398 385 508 528 378 380 114
-# Box to emulate async behaviour of FD[CP]*
+# Box to emulate async behaviour of FDC*
# Inputs: A S
# Outputs: Y
-$__ABC9_ASYNC 1000 0 2 1
+$__ABC9_ASYNC0 1000 1 2 1
+0 764
+
+# Box to emulate async behaviour of FDP*
+# Inputs: A S
+# Outputs: Y
+$__ABC9_ASYNC1 1001 1 2 1
0 764
# The following FD*.{CE,R,CLR,PRE) are offset by 46ps to
@@ -54,42 +60,42 @@ $__ABC9_ASYNC 1000 0 2 1
# Inputs: C CE D R \$currQ
# Outputs: Q
-FDRE 1001 1 5 1
+FDRE 1100 1 5 1
0 151 0 446 0
# Inputs: C CE D R \$currQ
# Outputs: Q
-FDRE_1 1002 1 5 1
+FDRE_1 1101 1 5 1
0 151 0 446 0
# Inputs: C CE CLR D \$currQ
# Outputs: Q
-FDCE 1003 1 5 1
+FDCE 1102 1 5 1
0 151 806 0 0
# Inputs: C CE CLR D \$currQ
# Outputs: Q
-FDCE_1 1004 1 5 1
+FDCE_1 1103 1 5 1
0 151 806 0 0
# Inputs: C CE D PRE \$currQ
# Outputs: Q
-FDPE 1005 1 5 1
+FDPE 1104 1 5 1
0 151 0 806 0
# Inputs: C CE D PRE \$currQ
# Outputs: Q
-FDPE_1 1006 1 5 1
+FDPE_1 1105 1 5 1
0 151 0 806 0
# Inputs: C CE D S \$currQ
# Outputs: Q
-FDSE 1007 1 5 1
+FDSE 1106 1 5 1
0 151 0 446 0
# Inputs: C CE D S \$currQ
# Outputs: Q
-FDSE_1 1008 1 5 1
+FDSE_1 1107 1 5 1
0 151 0 446 0
# SLICEM/A6LUT
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 7941a94cd..d7dff8975 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -283,7 +283,7 @@ endmodule
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
-(* abc9_box_id=1001, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1100, lib_whitebox, abc9_flop *)
module FDRE (
(* abc9_arrival=303 *)
output reg Q,
@@ -307,7 +307,7 @@ module FDRE (
endcase endgenerate
endmodule
-(* abc9_box_id=1002, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1101, lib_whitebox, abc9_flop *)
module FDRE_1 (
(* abc9_arrival=303 *)
output reg Q,
@@ -355,7 +355,7 @@ module FDRSE (
Q <= d;
endmodule
-(* abc9_box_id=1003, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1102, lib_whitebox, abc9_flop *)
module FDCE (
(* abc9_arrival=303 *)
output reg Q,
@@ -381,7 +381,7 @@ module FDCE (
endcase endgenerate
endmodule
-(* abc9_box_id=1004, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1103, lib_whitebox, abc9_flop *)
module FDCE_1 (
(* abc9_arrival=303 *)
output reg Q,
@@ -394,7 +394,7 @@ module FDCE_1 (
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
endmodule
-(* abc9_box_id=1005, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1104, lib_whitebox, abc9_flop *)
module FDPE (
(* abc9_arrival=303 *)
output reg Q,
@@ -420,7 +420,7 @@ module FDPE (
endcase endgenerate
endmodule
-(* abc9_box_id=1006, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1105, lib_whitebox, abc9_flop *)
module FDPE_1 (
(* abc9_arrival=303 *)
output reg Q,
@@ -433,7 +433,7 @@ module FDPE_1 (
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule
-(* abc9_box_id=1007, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1106, lib_whitebox, abc9_flop *)
module FDSE (
(* abc9_arrival=303 *)
output reg Q,
@@ -457,7 +457,7 @@ module FDSE (
endcase endgenerate
endmodule
-(* abc9_box_id=1008, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1107, lib_whitebox, abc9_flop *)
module FDSE_1 (
(* abc9_arrival=303 *)
output reg Q,
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-17 09:33:35 +0000