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-rw-r--r--techlibs/gowin/cells_map.v365
-rw-r--r--techlibs/gowin/synth_gowin.cc17
-rw-r--r--techlibs/xilinx/cells_map.v8
-rw-r--r--techlibs/xilinx/cells_sim.v797
-rw-r--r--techlibs/xilinx/cells_xtra.py68
-rw-r--r--techlibs/xilinx/cells_xtra.v590
-rw-r--r--techlibs/xilinx/synth_xilinx.cc17
7 files changed, 1117 insertions, 745 deletions
diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v
index 9845e56a7..aee912256 100644
--- a/techlibs/gowin/cells_map.v
+++ b/techlibs/gowin/cells_map.v
@@ -1,133 +1,282 @@
+`default_nettype none
//All DFF* have INIT, but the hardware is always initialised to the reset
//value regardless. The parameter is ignored.
-// DFFN D Flip-Flop with Negative-Edge Clock
-module \$_DFF_N_ (input D, C, output Q); DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
-// DFF D Flip-Flop
-module \$_DFF_P_ (input D, C, output Q); DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
+// DFFN D Flip-Flop with Negative-Edge Clock
+module \$_DFF_N_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, output Q);
+ generate
+ if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+ DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(1'b0));
+ else
+ DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));
+ endgenerate
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+
+// DFF D Flip-Flop
+module \$_DFF_P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, output Q);
+ generate
+ if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+ DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(1'b0));
+ else
+ DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));
+ endgenerate
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
-// DFFE D Flip-Flop with Clock Enable
-module \$_DFFE_PP_ (input D, C, E, output Q); DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E)); endmodule
-module \$_DFFE_PN_ (input D, C, E, output Q); DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E)); endmodule
+// DFFE D Flip-Flop with Clock Enable
+module \$_DFFE_PP_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
+ generate
+ if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+ DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E), .SET(1'b0));
+ else
+ DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));
+ endgenerate
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+
+module \$_DFFE_PN_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
+ generate
+ if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+ DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E), .SET(1'b0));
+ else
+ DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E));
+ endgenerate
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
-// DFFNE D Flip-Flop with Negative-Edge Clock and Clock Enable
-module \$_DFFE_NP_ (input D, C, E, output Q); DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E)); endmodule
-module \$_DFFE_NN_ (input D, C, E, output Q); DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E)); endmodule
+// DFFNE D Flip-Flop with Negative-Edge Clock and Clock Enable
+module \$_DFFE_NP_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
+ generate
+ if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+ DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E), .SET(1'b0));
+ else
+ DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));
+ endgenerate
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+
+module \$_DFFE_NN_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
+ generate
+ if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+ DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E), .SET(1'b0));
+ else
+ DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E));
+ endgenerate
+ wire _TECHMAP_REMOVEINIT_Q_ = 1;
+endmodule
+
+// DFFR D Flip-Flop with Synchronous Reset
+module \$__DFFS_PN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+ DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+endmodule
-// DFFR D Flip-Flop with Synchronous Reset
-module \$__DFFS_PN0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); endmodule
-module \$__DFFS_PP0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule
+module \$__DFFS_PP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+ DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+endmodule
-// DFFNR D Flip-Flop with Negative-Edge Clock and Synchronous Reset
-module \$__DFFS_NN0_ (input D, C, R, output Q); DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); endmodule
-module \$__DFFS_NP0_ (input D, C, R, output Q); DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule
+// DFFNR D Flip-Flop with Negative-Edge Clock and Synchronous Reset
+module \$__DFFS_NN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+ DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+endmodule
+module \$__DFFS_NP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+ DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+endmodule
-// DFFRE D Flip-Flop with Clock Enable and Synchronous Reset
-module \$__DFFSE_PN0 (input D, C, R, E, output Q); DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); endmodule
-module \$__DFFSE_PP0 (input D, C, R, E, output Q); DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E)); endmodule
+// DFFRE D Flip-Flop with Clock Enable and Synchronous Reset
+module \$__DFFSE_PN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+ DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+endmodule
+module \$__DFFSE_PP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+ DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+endmodule
-// DFFNRE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset
-module \$__DFFNSE_PN0 (input D, C, R, E, output Q); DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); endmodule
-module \$__DFFNSE_PP0 (input D, C, R, E, output Q); DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E)); endmodule
+// DFFNRE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset
+module \$__DFFSE_NN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+ DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+endmodule
+module \$__DFFSE_NP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+ DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+endmodule
-// DFFS D Flip-Flop with Synchronous Set
-module \$__DFFS_PN1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); endmodule
-module \$__DFFS_PP1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); endmodule
+// DFFS D Flip-Flop with Synchronous Set
+module \$__DFFS_PN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+ DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+endmodule
+module \$__DFFS_PP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+ DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+endmodule
-// DFFNS D Flip-Flop with Negative-Edge Clock and Synchronous Set
-module \$__DFFS_NN1_ (input D, C, R, output Q); DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); endmodule
-module \$__DFFS_NP1_ (input D, C, R, output Q); DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); endmodule
+// DFFNS D Flip-Flop with Negative-Edge Clock and Synchronous Set
+module \$__DFFS_NN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+ DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+endmodule
+module \$__DFFS_NP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+ DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+endmodule
-// DFFSE D Flip-Flop with Clock Enable and Synchronous Set
-module \$__DFFSE_PN1 (input D, C, R, E, output Q); DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); endmodule
-module \$__DFFSE_PP1 (input D, C, R, E, output Q); DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E)); endmodule
+// DFFSE D Flip-Flop with Clock Enable and Synchronous Set
+module \$__DFFSE_PN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+ DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+endmodule
+module \$__DFFSE_PP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+ DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+endmodule
-// DFFNSE D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set
-module \$__DFFSE_NN1 (input D, C, R, E, output Q); DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); endmodule
-module \$__DFFSE_NP1 (input D, C, R, E, output Q); DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E)); endmodule
+// DFFNSE D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set
+module \$__DFFSE_NN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+ DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+endmodule
+module \$__DFFSE_NP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+ DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+endmodule
-// DFFP D Flip-Flop with Asynchronous Preset
-module \$_DFF_PP1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); endmodule
-module \$_DFF_PN1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); endmodule
+// DFFP D Flip-Flop with Asynchronous Preset
+module \$_DFF_PP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+ DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+endmodule
+module \$_DFF_PN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+ DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+endmodule
-// DFFNP D Flip-Flop with Negative-Edge Clock and Asynchronous Preset
-module \$_DFF_NP1_ (input D, C, R, output Q); DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); endmodule
-module \$_DFF_NN1_ (input D, C, R, output Q); DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); endmodule
+// DFFNP D Flip-Flop with Negative-Edge Clock and Asynchronous Preset
+module \$_DFF_NP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+ DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+endmodule
+module \$_DFF_NN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+ DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+endmodule
-// DFFC D Flip-Flop with Asynchronous Clear
-module \$_DFF_PP0_ (input D, C, R, output Q); DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R)); endmodule
-module \$_DFF_PN0_ (input D, C, R, output Q); DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R)); endmodule
+// DFFC D Flip-Flop with Asynchronous Clear
+module \$_DFF_PP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+ DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+endmodule
+module \$_DFF_PN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+ DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+endmodule
-// DFFNC D Flip-Flop with Negative-Edge Clock and Asynchronous Clear
-module \$_DFF_NP0_ (input D, C, R, output Q); DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R)); endmodule
-module \$_DFF_NN0_ (input D, C, R, output Q); DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R)); endmodule
+// DFFNC D Flip-Flop with Negative-Edge Clock and Asynchronous Clear
+module \$_DFF_NP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+ DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+endmodule
+module \$_DFF_NN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+ DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+endmodule
-// DFFPE D Flip-Flop with Clock Enable and Asynchronous Preset
-module \$__DFFE_PP1 (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); endmodule
-module \$__DFFE_PN1 (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); endmodule
+// DFFPE D Flip-Flop with Clock Enable and Asynchronous Preset
+module \$__DFFE_PP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+ DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+endmodule
+module \$__DFFE_PN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+ DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+endmodule
-// DFFNPE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset
-module \$__DFFE_NP1 (input D, C, R, E, output Q); DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); endmodule
-module \$__DFFE_NN1 (input D, C, R, E, output Q); DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); endmodule
+// DFFNPE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset
+module \$__DFFE_NP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+ DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+endmodule
+module \$__DFFE_NN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+ DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
+endmodule
-// DFFCE D Flip-Flop with Clock Enable and Asynchronous Clear
-module \$__DFFE_PP0 (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); endmodule
-module \$__DFFE_PN0 (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); endmodule
+// DFFCE D Flip-Flop with Clock Enable and Asynchronous Clear
+module \$__DFFE_PP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+ DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+endmodule
+module \$__DFFE_PN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+ DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+endmodule
-// DFFNCE D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear
-module \$__DFFE_NP0 (input D, C, R, E, output Q); DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); endmodule
-module \$__DFFE_NN0 (input D, C, R, E, output Q); DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); endmodule
+// DFFNCE D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear
+module \$__DFFE_NP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+ DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+endmodule
+module \$__DFFE_NN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+ DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E));
+ wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
+endmodule
module \$lut (A, Y);
- parameter WIDTH = 0;
- parameter LUT = 0;
-
- input [WIDTH-1:0] A;
- output Y;
-
- generate
- if (WIDTH == 1) begin
- LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
- .I0(A[0]));
- end else
- if (WIDTH == 2) begin
- LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
- .I0(A[0]), .I1(A[1]));
- end else
- if (WIDTH == 3) begin
- LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
- .I0(A[0]), .I1(A[1]), .I2(A[2]));
- end else
- if (WIDTH == 4) begin
- LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
- .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
- end else
- if (WIDTH == 5) begin
- wire f0, f1;
- \$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0));
- \$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1));
- MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[4]), .O(Y));
- end else
- if (WIDTH == 6) begin
- wire f0, f1;
- \$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0));
- \$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1));
- MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[5]), .O(Y));
- end else
- if (WIDTH == 7) begin
- wire f0, f1;
- \$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0));
- \$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1));
- MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[6]), .O(Y));
- end else
- if (WIDTH == 8) begin
- wire f0, f1;
- \$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0));
- \$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1));
- MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[7]), .O(Y));
- end else begin
- wire _TECHMAP_FAIL_ = 1;
- end
- endgenerate
+ parameter WIDTH = 0;
+ parameter LUT = 0;
+
+ input [WIDTH-1:0] A;
+ output Y;
+
+ generate
+ if (WIDTH == 1) begin
+ LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
+ .I0(A[0]));
+ end else
+ if (WIDTH == 2) begin
+ LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
+ .I0(A[0]), .I1(A[1]));
+ end else
+ if (WIDTH == 3) begin
+ LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
+ .I0(A[0]), .I1(A[1]), .I2(A[2]));
+ end else
+ if (WIDTH == 4) begin
+ LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
+ .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
+ end else
+ if (WIDTH == 5) begin
+ wire f0, f1;
+ \$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0));
+ \$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1));
+ MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[4]), .O(Y));
+ end else
+ if (WIDTH == 6) begin
+ wire f0, f1;
+ \$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0));
+ \$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1));
+ MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[5]), .O(Y));
+ end else
+ if (WIDTH == 7) begin
+ wire f0, f1;
+ \$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0));
+ \$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1));
+ MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[6]), .O(Y));
+ end else
+ if (WIDTH == 8) begin
+ wire f0, f1;
+ \$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0));
+ \$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1));
+ MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[7]), .O(Y));
+ end else begin
+ wire _TECHMAP_FAIL_ = 1;
+ end
+ endgenerate
endmodule
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index 3c1426414..6cf058f29 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -67,6 +67,9 @@ struct SynthGowinPass : public ScriptPass
log(" -nowidelut\n");
log(" do not use muxes to implement LUTs larger than LUT4s\n");
log("\n");
+ log(" -noiopads\n");
+ log(" do not emit IOB at top level ports\n");
+ log("\n");
log(" -abc9\n");
log(" use new ABC9 flow (EXPERIMENTAL)\n");
log("\n");
@@ -77,7 +80,7 @@ struct SynthGowinPass : public ScriptPass
}
string top_opt, vout_file;
- bool retime, nobram, nodram, flatten, nodffe, nowidelut, abc9;
+ bool retime, nobram, nodram, flatten, nodffe, nowidelut, abc9, noiopads;
void clear_flags() YS_OVERRIDE
{
@@ -90,6 +93,7 @@ struct SynthGowinPass : public ScriptPass
nodram = false;
nowidelut = false;
abc9 = false;
+ noiopads = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -144,6 +148,10 @@ struct SynthGowinPass : public ScriptPass
abc9 = true;
continue;
}
+ if (args[argidx] == "-noiopads") {
+ noiopads = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
@@ -208,7 +216,7 @@ struct SynthGowinPass : public ScriptPass
if (check_label("map_ffs"))
{
run("dffsr2dff");
- run("dff2dffs");
+ run("dff2dffs -match-init");
run("opt_clean");
if (!nodffe)
run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
@@ -236,8 +244,9 @@ struct SynthGowinPass : public ScriptPass
run("techmap -map +/gowin/cells_map.v");
run("setundef -undriven -params -zero");
run("hilomap -singleton -hicell VCC V -locell GND G");
- run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O "
- "-toutpad TBUF OEN:I:O -tinoutpad IOBUF OEN:O:I:IO", "(unless -noiopads)");
+ if (!noiopads || help_mode)
+ run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O "
+ "-toutpad TBUF OEN:I:O -tinoutpad IOBUF OEN:O:I:IO", "(unless -noiopads)");
run("clean");
}
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index a15884ec4..de2068bc5 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -363,3 +363,11 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
else
MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
endmodule
+
+module \$__XILINX_TINOUTPAD (input I, OE, output O, inout IO);
+ IOBUF _TECHMAP_REPLACE_ (.I(I), .O(O), .T(~OE), .IO(IO));
+endmodule
+
+module \$__XILINX_TOUTPAD (input I, OE, output O);
+ OBUFT _TECHMAP_REPLACE_ (.I(I), .O(O), .T(~OE));
+endmodule
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 1be43f9d4..3ed0759db 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -471,6 +471,473 @@ module LDPE (
else if (GE && g) Q = D;
endmodule
+// LUTRAM.
+
+// Single port.
+
+module RAM16X1S (
+ output O,
+ input A0, A1, A2, A3,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [15:0] INIT = 16'h0000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [3:0] a = {A3, A2, A1, A0};
+ reg [15:0] mem = INIT;
+ assign O = mem[a];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk) if (WE) mem[a] <= D;
+endmodule
+
+module RAM16X1S_1 (
+ output O,
+ input A0, A1, A2, A3,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [15:0] INIT = 16'h0000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [3:0] a = {A3, A2, A1, A0};
+ reg [15:0] mem = INIT;
+ assign O = mem[a];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(negedge clk) if (WE) mem[a] <= D;
+endmodule
+
+module RAM32X1S (
+ output O,
+ input A0, A1, A2, A3, A4,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [31:0] INIT = 32'h00000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [4:0] a = {A4, A3, A2, A1, A0};
+ reg [31:0] mem = INIT;
+ assign O = mem[a];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk) if (WE) mem[a] <= D;
+endmodule
+
+module RAM32X1S_1 (
+ output O,
+ input A0, A1, A2, A3, A4,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [31:0] INIT = 32'h00000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [4:0] a = {A4, A3, A2, A1, A0};
+ reg [31:0] mem = INIT;
+ assign O = mem[a];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(negedge clk) if (WE) mem[a] <= D;
+endmodule
+
+module RAM64X1S (
+ output O,
+ input A0, A1, A2, A3, A4, A5,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [63:0] INIT = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [5:0] a = {A5, A4, A3, A2, A1, A0};
+ reg [63:0] mem = INIT;
+ assign O = mem[a];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk) if (WE) mem[a] <= D;
+endmodule
+
+module RAM64X1S_1 (
+ output O,
+ input A0, A1, A2, A3, A4, A5,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [63:0] INIT = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [5:0] a = {A5, A4, A3, A2, A1, A0};
+ reg [63:0] mem = INIT;
+ assign O = mem[a];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(negedge clk) if (WE) mem[a] <= D;
+endmodule
+
+module RAM128X1S (
+ output O,
+ input A0, A1, A2, A3, A4, A5, A6,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [127:0] INIT = 128'h00000000000000000000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [6:0] a = {A6, A5, A4, A3, A2, A1, A0};
+ reg [127:0] mem = INIT;
+ assign O = mem[a];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk) if (WE) mem[a] <= D;
+endmodule
+
+module RAM128X1S_1 (
+ output O,
+ input A0, A1, A2, A3, A4, A5, A6,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [127:0] INIT = 128'h00000000000000000000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [6:0] a = {A6, A5, A4, A3, A2, A1, A0};
+ reg [127:0] mem = INIT;
+ assign O = mem[a];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(negedge clk) if (WE) mem[a] <= D;
+endmodule
+
+module RAM256X1S (
+ output O,
+ input [7:0] A,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [255:0] INIT = 256'h0;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ reg [255:0] mem = INIT;
+ assign O = mem[A];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk) if (WE) mem[A] <= D;
+endmodule
+
+module RAM512X1S (
+ output O,
+ input [8:0] A,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [511:0] INIT = 512'h0;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ reg [511:0] mem = INIT;
+ assign O = mem[A];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk) if (WE) mem[A] <= D;
+endmodule
+
+// Single port, wide.
+
+module RAM16X2S (
+ output O0, O1,
+ input A0, A1, A2, A3,
+ input D0, D1,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [15:0] INIT_00 = 16'h0000;
+ parameter [15:0] INIT_01 = 16'h0000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [3:0] a = {A3, A2, A1, A0};
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ reg [15:0] mem0 = INIT_00;
+ reg [15:0] mem1 = INIT_01;
+ assign O0 = mem0[a];
+ assign O1 = mem1[a];
+ always @(posedge clk)
+ if (WE) begin
+ mem0[a] <= D0;
+ mem1[a] <= D1;
+ end
+endmodule
+
+module RAM32X2S (
+ output O0, O1,
+ input A0, A1, A2, A3, A4,
+ input D0, D1,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [31:0] INIT_00 = 32'h00000000;
+ parameter [31:0] INIT_01 = 32'h00000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [4:0] a = {A4, A3, A2, A1, A0};
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ reg [31:0] mem0 = INIT_00;
+ reg [31:0] mem1 = INIT_01;
+ assign O0 = mem0[a];
+ assign O1 = mem1[a];
+ always @(posedge clk)
+ if (WE) begin
+ mem0[a] <= D0;
+ mem1[a] <= D1;
+ end
+endmodule
+
+module RAM64X2S (
+ output O0, O1,
+ input A0, A1, A2, A3, A4, A5,
+ input D0, D1,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [63:0] INIT_00 = 64'h0000000000000000;
+ parameter [63:0] INIT_01 = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [5:0] a = {A5, A3, A2, A1, A0};
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ reg [63:0] mem0 = INIT_00;
+ reg [63:0] mem1 = INIT_01;
+ assign O0 = mem0[a];
+ assign O1 = mem1[a];
+ always @(posedge clk)
+ if (WE) begin
+ mem0[a] <= D0;
+ mem1[a] <= D1;
+ end
+endmodule
+
+module RAM16X4S (
+ output O0, O1, O2, O3,
+ input A0, A1, A2, A3,
+ input D0, D1, D2, D3,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [15:0] INIT_00 = 16'h0000;
+ parameter [15:0] INIT_01 = 16'h0000;
+ parameter [15:0] INIT_02 = 16'h0000;
+ parameter [15:0] INIT_03 = 16'h0000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [3:0] a = {A3, A2, A1, A0};
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ reg [15:0] mem0 = INIT_00;
+ reg [15:0] mem1 = INIT_01;
+ reg [15:0] mem2 = INIT_02;
+ reg [15:0] mem3 = INIT_03;
+ assign O0 = mem0[a];
+ assign O1 = mem1[a];
+ assign O2 = mem2[a];
+ assign O3 = mem3[a];
+ always @(posedge clk)
+ if (WE) begin
+ mem0[a] <= D0;
+ mem1[a] <= D1;
+ mem2[a] <= D2;
+ mem3[a] <= D3;
+ end
+endmodule
+
+module RAM32X4S (
+ output O0, O1, O2, O3,
+ input A0, A1, A2, A3, A4,
+ input D0, D1, D2, D3,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [31:0] INIT_00 = 32'h00000000;
+ parameter [31:0] INIT_01 = 32'h00000000;
+ parameter [31:0] INIT_02 = 32'h00000000;
+ parameter [31:0] INIT_03 = 32'h00000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [4:0] a = {A4, A3, A2, A1, A0};
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ reg [31:0] mem0 = INIT_00;
+ reg [31:0] mem1 = INIT_01;
+ reg [31:0] mem2 = INIT_02;
+ reg [31:0] mem3 = INIT_03;
+ assign O0 = mem0[a];
+ assign O1 = mem1[a];
+ assign O2 = mem2[a];
+ assign O3 = mem3[a];
+ always @(posedge clk)
+ if (WE) begin
+ mem0[a] <= D0;
+ mem1[a] <= D1;
+ mem2[a] <= D2;
+ mem3[a] <= D3;
+ end
+endmodule
+
+module RAM16X8S (
+ output [7:0] O,
+ input A0, A1, A2, A3,
+ input [7:0] D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [15:0] INIT_00 = 16'h0000;
+ parameter [15:0] INIT_01 = 16'h0000;
+ parameter [15:0] INIT_02 = 16'h0000;
+ parameter [15:0] INIT_03 = 16'h0000;
+ parameter [15:0] INIT_04 = 16'h0000;
+ parameter [15:0] INIT_05 = 16'h0000;
+ parameter [15:0] INIT_06 = 16'h0000;
+ parameter [15:0] INIT_07 = 16'h0000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [3:0] a = {A3, A2, A1, A0};
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ reg [15:0] mem0 = INIT_00;
+ reg [15:0] mem1 = INIT_01;
+ reg [15:0] mem2 = INIT_02;
+ reg [15:0] mem3 = INIT_03;
+ reg [15:0] mem4 = INIT_04;
+ reg [15:0] mem5 = INIT_05;
+ reg [15:0] mem6 = INIT_06;
+ reg [15:0] mem7 = INIT_07;
+ assign O[0] = mem0[a];
+ assign O[1] = mem1[a];
+ assign O[2] = mem2[a];
+ assign O[3] = mem3[a];
+ assign O[4] = mem4[a];
+ assign O[5] = mem5[a];
+ assign O[6] = mem6[a];
+ assign O[7] = mem7[a];
+ always @(posedge clk)
+ if (WE) begin
+ mem0[a] <= D[0];
+ mem1[a] <= D[1];
+ mem2[a] <= D[2];
+ mem3[a] <= D[3];
+ mem4[a] <= D[4];
+ mem5[a] <= D[5];
+ mem6[a] <= D[6];
+ mem7[a] <= D[7];
+ end
+endmodule
+
+module RAM32X8S (
+ output [7:0] O,
+ input A0, A1, A2, A3, A4,
+ input [7:0] D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [31:0] INIT_00 = 32'h00000000;
+ parameter [31:0] INIT_01 = 32'h00000000;
+ parameter [31:0] INIT_02 = 32'h00000000;
+ parameter [31:0] INIT_03 = 32'h00000000;
+ parameter [31:0] INIT_04 = 32'h00000000;
+ parameter [31:0] INIT_05 = 32'h00000000;
+ parameter [31:0] INIT_06 = 32'h00000000;
+ parameter [31:0] INIT_07 = 32'h00000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [4:0] a = {A4, A3, A2, A1, A0};
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ reg [31:0] mem0 = INIT_00;
+ reg [31:0] mem1 = INIT_01;
+ reg [31:0] mem2 = INIT_02;
+ reg [31:0] mem3 = INIT_03;
+ reg [31:0] mem4 = INIT_04;
+ reg [31:0] mem5 = INIT_05;
+ reg [31:0] mem6 = INIT_06;
+ reg [31:0] mem7 = INIT_07;
+ assign O[0] = mem0[a];
+ assign O[1] = mem1[a];
+ assign O[2] = mem2[a];
+ assign O[3] = mem3[a];
+ assign O[4] = mem4[a];
+ assign O[5] = mem5[a];
+ assign O[6] = mem6[a];
+ assign O[7] = mem7[a];
+ always @(posedge clk)
+ if (WE) begin
+ mem0[a] <= D[0];
+ mem1[a] <= D[1];
+ mem2[a] <= D[2];
+ mem3[a] <= D[3];
+ mem4[a] <= D[4];
+ mem5[a] <= D[5];
+ mem6[a] <= D[6];
+ mem7[a] <= D[7];
+ end
+endmodule
+
+// Dual port.
+
+module RAM16X1D (
+ output DPO, SPO,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE,
+ input A0, A1, A2, A3,
+ input DPRA0, DPRA1, DPRA2, DPRA3
+);
+ parameter INIT = 16'h0;
+ parameter IS_WCLK_INVERTED = 1'b0;
+ wire [3:0] a = {A3, A2, A1, A0};
+ wire [3:0] dpra = {DPRA3, DPRA2, DPRA1, DPRA0};
+ reg [15:0] mem = INIT;
+ assign SPO = mem[a];
+ assign DPO = mem[dpra];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk) if (WE) mem[a] <= D;
+endmodule
+
+module RAM16X1D_1 (
+ output DPO, SPO,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE,
+ input A0, A1, A2, A3,
+ input DPRA0, DPRA1, DPRA2, DPRA3
+);
+ parameter INIT = 16'h0;
+ parameter IS_WCLK_INVERTED = 1'b0;
+ wire [3:0] a = {A3, A2, A1, A0};
+ wire [3:0] dpra = {DPRA3, DPRA2, DPRA1, DPRA0};
+ reg [15:0] mem = INIT;
+ assign SPO = mem[a];
+ assign DPO = mem[dpra];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(negedge clk) if (WE) mem[a] <= D;
+endmodule
+
module RAM32X1D (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
(* abc9_arrival=1153 *)
@@ -494,6 +961,29 @@ module RAM32X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
+module RAM32X1D_1 (
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+ (* abc9_arrival=1153 *)
+ output DPO, SPO,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE,
+ input A0, A1, A2, A3, A4,
+ input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
+);
+ parameter INIT = 32'h0;
+ parameter IS_WCLK_INVERTED = 1'b0;
+ wire [4:0] a = {A4, A3, A2, A1, A0};
+ wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
+ reg [31:0] mem = INIT;
+ assign SPO = mem[a];
+ assign DPO = mem[dpra];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(negedge clk) if (WE) mem[a] <= D;
+endmodule
+
module RAM64X1D (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
(* abc9_arrival=1153 *)
@@ -517,6 +1007,29 @@ module RAM64X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
+module RAM64X1D_1 (
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+ (* abc9_arrival=1153 *)
+ output DPO, SPO,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE,
+ input A0, A1, A2, A3, A4, A5,
+ input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
+);
+ parameter INIT = 64'h0;
+ parameter IS_WCLK_INVERTED = 1'b0;
+ wire [5:0] a = {A5, A4, A3, A2, A1, A0};
+ wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
+ reg [63:0] mem = INIT;
+ assign SPO = mem[a];
+ assign DPO = mem[dpra];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(negedge clk) if (WE) mem[a] <= D;
+endmodule
+
module RAM128X1D (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
(* abc9_arrival=1153 *)
@@ -537,6 +1050,290 @@ module RAM128X1D (
always @(posedge clk) if (WE) mem[A] <= D;
endmodule
+module RAM256X1D (
+ output DPO, SPO,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE,
+ input [7:0] A, DPRA
+);
+ parameter INIT = 256'h0;
+ parameter IS_WCLK_INVERTED = 1'b0;
+ reg [255:0] mem = INIT;
+ assign SPO = mem[A];
+ assign DPO = mem[DPRA];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk) if (WE) mem[A] <= D;
+endmodule
+
+// Multi port.
+
+module RAM32M (
+ output [1:0] DOA,
+ output [1:0] DOB,
+ output [1:0] DOC,
+ output [1:0] DOD,
+ input [4:0] ADDRA,
+ input [4:0] ADDRB,
+ input [4:0] ADDRC,
+ input [4:0] ADDRD,
+ input [1:0] DIA,
+ input [1:0] DIB,
+ input [1:0] DIC,
+ input [1:0] DID,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [63:0] INIT_A = 64'h0000000000000000;
+ parameter [63:0] INIT_B = 64'h0000000000000000;
+ parameter [63:0] INIT_C = 64'h0000000000000000;
+ parameter [63:0] INIT_D = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ reg [63:0] mem_a = INIT_A;
+ reg [63:0] mem_b = INIT_B;
+ reg [63:0] mem_c = INIT_C;
+ reg [63:0] mem_d = INIT_D;
+ assign DOA = mem_a[2*ADDRA+:2];
+ assign DOB = mem_b[2*ADDRB+:2];
+ assign DOC = mem_c[2*ADDRC+:2];
+ assign DOD = mem_d[2*ADDRD+:2];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk)
+ if (WE) begin
+ mem_a[2*ADDRD+:2] <= DIA;
+ mem_b[2*ADDRD+:2] <= DIB;
+ mem_c[2*ADDRD+:2] <= DIC;
+ mem_d[2*ADDRD+:2] <= DID;
+ end
+endmodule
+
+module RAM32M16 (
+ output [1:0] DOA,
+ output [1:0] DOB,
+ output [1:0] DOC,
+ output [1:0] DOD,
+ output [1:0] DOE,
+ output [1:0] DOF,
+ output [1:0] DOG,
+ output [1:0] DOH,
+ input [4:0] ADDRA,
+ input [4:0] ADDRB,
+ input [4:0] ADDRC,
+ input [4:0] ADDRD,
+ input [4:0] ADDRE,
+ input [4:0] ADDRF,
+ input [4:0] ADDRG,
+ input [4:0] ADDRH,
+ input [1:0] DIA,
+ input [1:0] DIB,
+ input [1:0] DIC,
+ input [1:0] DID,
+ input [1:0] DIE,
+ input [1:0] DIF,
+ input [1:0] DIG,
+ input [1:0] DIH,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [63:0] INIT_A = 64'h0000000000000000;
+ parameter [63:0] INIT_B = 64'h0000000000000000;
+ parameter [63:0] INIT_C = 64'h0000000000000000;
+ parameter [63:0] INIT_D = 64'h0000000000000000;
+ parameter [63:0] INIT_E = 64'h0000000000000000;
+ parameter [63:0] INIT_F = 64'h0000000000000000;
+ parameter [63:0] INIT_G = 64'h0000000000000000;
+ parameter [63:0] INIT_H = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ reg [63:0] mem_a = INIT_A;
+ reg [63:0] mem_b = INIT_B;
+ reg [63:0] mem_c = INIT_C;
+ reg [63:0] mem_d = INIT_D;
+ reg [63:0] mem_e = INIT_E;
+ reg [63:0] mem_f = INIT_F;
+ reg [63:0] mem_g = INIT_G;
+ reg [63:0] mem_h = INIT_H;
+ assign DOA = mem_a[2*ADDRA+:2];
+ assign DOB = mem_b[2*ADDRB+:2];
+ assign DOC = mem_c[2*ADDRC+:2];
+ assign DOD = mem_d[2*ADDRD+:2];
+ assign DOE = mem_e[2*ADDRE+:2];
+ assign DOF = mem_f[2*ADDRF+:2];
+ assign DOG = mem_g[2*ADDRG+:2];
+ assign DOH = mem_h[2*ADDRH+:2];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk)
+ if (WE) begin
+ mem_a[2*ADDRH+:2] <= DIA;
+ mem_b[2*ADDRH+:2] <= DIB;
+ mem_c[2*ADDRH+:2] <= DIC;
+ mem_d[2*ADDRH+:2] <= DID;
+ mem_e[2*ADDRH+:2] <= DIE;
+ mem_f[2*ADDRH+:2] <= DIF;
+ mem_g[2*ADDRH+:2] <= DIG;
+ mem_h[2*ADDRH+:2] <= DIH;
+ end
+endmodule
+
+module RAM64M (
+ output DOA,
+ output DOB,
+ output DOC,
+ output DOD,
+ input [4:0] ADDRA,
+ input [4:0] ADDRB,
+ input [4:0] ADDRC,
+ input [4:0] ADDRD,
+ input DIA,
+ input DIB,
+ input DIC,
+ input DID,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [63:0] INIT_A = 64'h0000000000000000;
+ parameter [63:0] INIT_B = 64'h0000000000000000;
+ parameter [63:0] INIT_C = 64'h0000000000000000;
+ parameter [63:0] INIT_D = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ reg [63:0] mem_a = INIT_A;
+ reg [63:0] mem_b = INIT_B;
+ reg [63:0] mem_c = INIT_C;
+ reg [63:0] mem_d = INIT_D;
+ assign DOA = mem_a[ADDRA];
+ assign DOB = mem_b[ADDRB];
+ assign DOC = mem_c[ADDRC];
+ assign DOD = mem_d[ADDRD];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk)
+ if (WE) begin
+ mem_a[ADDRD] <= DIA;
+ mem_b[ADDRD] <= DIB;
+ mem_c[ADDRD] <= DIC;
+ mem_d[ADDRD] <= DID;
+ end
+endmodule
+
+module RAM64M8 (
+ output DOA,
+ output DOB,
+ output DOC,
+ output DOD,
+ output DOE,
+ output DOF,
+ output DOG,
+ output DOH,
+ input [4:0] ADDRA,
+ input [4:0] ADDRB,
+ input [4:0] ADDRC,
+ input [4:0] ADDRD,
+ input [4:0] ADDRE,
+ input [4:0] ADDRF,
+ input [4:0] ADDRG,
+ input [4:0] ADDRH,
+ input DIA,
+ input DIB,
+ input DIC,
+ input DID,
+ input DIE,
+ input DIF,
+ input DIG,
+ input DIH,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [63:0] INIT_A = 64'h0000000000000000;
+ parameter [63:0] INIT_B = 64'h0000000000000000;
+ parameter [63:0] INIT_C = 64'h0000000000000000;
+ parameter [63:0] INIT_D = 64'h0000000000000000;
+ parameter [63:0] INIT_E = 64'h0000000000000000;
+ parameter [63:0] INIT_F = 64'h0000000000000000;
+ parameter [63:0] INIT_G = 64'h0000000000000000;
+ parameter [63:0] INIT_H = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ reg [63:0] mem_a = INIT_A;
+ reg [63:0] mem_b = INIT_B;
+ reg [63:0] mem_c = INIT_C;
+ reg [63:0] mem_d = INIT_D;
+ reg [63:0] mem_e = INIT_E;
+ reg [63:0] mem_f = INIT_F;
+ reg [63:0] mem_g = INIT_G;
+ reg [63:0] mem_h = INIT_H;
+ assign DOA = mem_a[ADDRA];
+ assign DOB = mem_b[ADDRB];
+ assign DOC = mem_c[ADDRC];
+ assign DOD = mem_d[ADDRD];
+ assign DOE = mem_e[ADDRE];
+ assign DOF = mem_f[ADDRF];
+ assign DOG = mem_g[ADDRG];
+ assign DOH = mem_h[ADDRH];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk)
+ if (WE) begin
+ mem_a[ADDRH] <= DIA;
+ mem_b[ADDRH] <= DIB;
+ mem_c[ADDRH] <= DIC;
+ mem_d[ADDRH] <= DID;
+ mem_e[ADDRH] <= DIE;
+ mem_f[ADDRH] <= DIF;
+ mem_g[ADDRH] <= DIG;
+ mem_h[ADDRH] <= DIH;
+ end
+endmodule
+
+// ROM.
+
+module ROM16X1 (
+ output O,
+ input A0, A1, A2, A3
+);
+ parameter [15:0] INIT = 16'h0;
+ assign O = INIT[{A3, A2, A1, A0}];
+endmodule
+
+module ROM32X1 (
+ output O,
+ input A0, A1, A2, A3, A4
+);
+ parameter [31:0] INIT = 32'h0;
+ assign O = INIT[{A4, A3, A2, A1, A0}];
+endmodule
+
+module ROM64X1 (
+ output O,
+ input A0, A1, A2, A3, A4, A5
+);
+ parameter [63:0] INIT = 64'h0;
+ assign O = INIT[{A5, A4, A3, A2, A1, A0}];
+endmodule
+
+module ROM128X1 (
+ output O,
+ input A0, A1, A2, A3, A4, A5, A6
+);
+ parameter [127:0] INIT = 128'h0;
+ assign O = INIT[{A6, A5, A4, A3, A2, A1, A0}];
+endmodule
+
+module ROM256X1 (
+ output O,
+ input A0, A1, A2, A3, A4, A5, A6, A7
+);
+ parameter [255:0] INIT = 256'h0;
+ assign O = INIT[{A7, A6, A5, A4, A3, A2, A1, A0}];
+endmodule
+
+// Shift registers.
+
module SRL16E (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
(* abc9_arrival=1472 *)
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py
index 01e7101d1..e4c580b9d 100644
--- a/techlibs/xilinx/cells_xtra.py
+++ b/techlibs/xilinx/cells_xtra.py
@@ -28,40 +28,40 @@ CELLS = [
# - UG974 (Ultrascale)
# CLB -- RAM/ROM.
- Cell('RAM16X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM16X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM128X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM512X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM16X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM16X4S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM32X4S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM16X8S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM32X8S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM16X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM16X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}),
- #Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM32X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}),
- #Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM64X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}),
- #Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM256X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM32M16', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM64M8', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('ROM16X1'),
- Cell('ROM32X1'),
- Cell('ROM64X1'),
- Cell('ROM128X1'),
- Cell('ROM256X1'),
+ # Cell('RAM16X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM16X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM128X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM512X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM16X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM16X4S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM32X4S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM16X8S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM32X8S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM16X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM16X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM32X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM64X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM256X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM32M16', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM64M8', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('ROM16X1'),
+ # Cell('ROM32X1'),
+ # Cell('ROM64X1'),
+ # Cell('ROM128X1'),
+ # Cell('ROM256X1'),
# CLB -- registers/latches.
# Virtex 1/2/4/5, Spartan 3.
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index 00a8a5f8a..8ac596459 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -1,595 +1,5 @@
// Created by cells_xtra.py from Xilinx models
-module RAM16X1S (...);
- parameter [15:0] INIT = 16'h0000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM16X1S_1 (...);
- parameter [15:0] INIT = 16'h0000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM32X1S (...);
- parameter [31:0] INIT = 32'h00000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM32X1S_1 (...);
- parameter [31:0] INIT = 32'h00000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM64X1S (...);
- parameter [63:0] INIT = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM64X1S_1 (...);
- parameter [63:0] INIT = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM128X1S (...);
- parameter [127:0] INIT = 128'h00000000000000000000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input A6;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM128X1S_1 (...);
- parameter [127:0] INIT = 128'h00000000000000000000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input A6;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM256X1S (...);
- parameter [255:0] INIT = 256'h0;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input [7:0] A;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM512X1S (...);
- parameter [511:0] INIT = 512'h0;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input [8:0] A;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM16X2S (...);
- parameter [15:0] INIT_00 = 16'h0000;
- parameter [15:0] INIT_01 = 16'h0000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O0;
- output O1;
- input A0;
- input A1;
- input A2;
- input A3;
- input D0;
- input D1;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM32X2S (...);
- parameter [31:0] INIT_00 = 32'h00000000;
- parameter [31:0] INIT_01 = 32'h00000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O0;
- output O1;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input D0;
- input D1;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM64X2S (...);
- parameter [63:0] INIT_00 = 64'h0000000000000000;
- parameter [63:0] INIT_01 = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O0;
- output O1;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input D0;
- input D1;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM16X4S (...);
- parameter [15:0] INIT_00 = 16'h0000;
- parameter [15:0] INIT_01 = 16'h0000;
- parameter [15:0] INIT_02 = 16'h0000;
- parameter [15:0] INIT_03 = 16'h0000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O0;
- output O1;
- output O2;
- output O3;
- input A0;
- input A1;
- input A2;
- input A3;
- input D0;
- input D1;
- input D2;
- input D3;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM32X4S (...);
- parameter [31:0] INIT_00 = 32'h00000000;
- parameter [31:0] INIT_01 = 32'h00000000;
- parameter [31:0] INIT_02 = 32'h00000000;
- parameter [31:0] INIT_03 = 32'h00000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O0;
- output O1;
- output O2;
- output O3;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input D0;
- input D1;
- input D2;
- input D3;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM16X8S (...);
- parameter [15:0] INIT_00 = 16'h0000;
- parameter [15:0] INIT_01 = 16'h0000;
- parameter [15:0] INIT_02 = 16'h0000;
- parameter [15:0] INIT_03 = 16'h0000;
- parameter [15:0] INIT_04 = 16'h0000;
- parameter [15:0] INIT_05 = 16'h0000;
- parameter [15:0] INIT_06 = 16'h0000;
- parameter [15:0] INIT_07 = 16'h0000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output [7:0] O;
- input A0;
- input A1;
- input A2;
- input A3;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
- input [7:0] D;
-endmodule
-
-module RAM32X8S (...);
- parameter [31:0] INIT_00 = 32'h00000000;
- parameter [31:0] INIT_01 = 32'h00000000;
- parameter [31:0] INIT_02 = 32'h00000000;
- parameter [31:0] INIT_03 = 32'h00000000;
- parameter [31:0] INIT_04 = 32'h00000000;
- parameter [31:0] INIT_05 = 32'h00000000;
- parameter [31:0] INIT_06 = 32'h00000000;
- parameter [31:0] INIT_07 = 32'h00000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output [7:0] O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
- input [7:0] D;
-endmodule
-
-module RAM16X1D (...);
- parameter [15:0] INIT = 16'h0000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output DPO;
- output SPO;
- input A0;
- input A1;
- input A2;
- input A3;
- input D;
- input DPRA0;
- input DPRA1;
- input DPRA2;
- input DPRA3;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM16X1D_1 (...);
- parameter [15:0] INIT = 16'h0000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output DPO;
- output SPO;
- input A0;
- input A1;
- input A2;
- input A3;
- input D;
- input DPRA0;
- input DPRA1;
- input DPRA2;
- input DPRA3;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM32X1D_1 (...);
- parameter [31:0] INIT = 32'h00000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output DPO;
- output SPO;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input D;
- input DPRA0;
- input DPRA1;
- input DPRA2;
- input DPRA3;
- input DPRA4;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM64X1D_1 (...);
- parameter [63:0] INIT = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output DPO;
- output SPO;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input D;
- input DPRA0;
- input DPRA1;
- input DPRA2;
- input DPRA3;
- input DPRA4;
- input DPRA5;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM256X1D (...);
- parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output DPO;
- output SPO;
- input [7:0] A;
- input D;
- input [7:0] DPRA;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM32M (...);
- parameter [63:0] INIT_A = 64'h0000000000000000;
- parameter [63:0] INIT_B = 64'h0000000000000000;
- parameter [63:0] INIT_C = 64'h0000000000000000;
- parameter [63:0] INIT_D = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output [1:0] DOA;
- output [1:0] DOB;
- output [1:0] DOC;
- output [1:0] DOD;
- input [4:0] ADDRA;
- input [4:0] ADDRB;
- input [4:0] ADDRC;
- input [4:0] ADDRD;
- input [1:0] DIA;
- input [1:0] DIB;
- input [1:0] DIC;
- input [1:0] DID;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM32M16 (...);
- parameter [63:0] INIT_A = 64'h0000000000000000;
- parameter [63:0] INIT_B = 64'h0000000000000000;
- parameter [63:0] INIT_C = 64'h0000000000000000;
- parameter [63:0] INIT_D = 64'h0000000000000000;
- parameter [63:0] INIT_E = 64'h0000000000000000;
- parameter [63:0] INIT_F = 64'h0000000000000000;
- parameter [63:0] INIT_G = 64'h0000000000000000;
- parameter [63:0] INIT_H = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output [1:0] DOA;
- output [1:0] DOB;
- output [1:0] DOC;
- output [1:0] DOD;
- output [1:0] DOE;
- output [1:0] DOF;
- output [1:0] DOG;
- output [1:0] DOH;
- input [4:0] ADDRA;
- input [4:0] ADDRB;
- input [4:0] ADDRC;
- input [4:0] ADDRD;
- input [4:0] ADDRE;
- input [4:0] ADDRF;
- input [4:0] ADDRG;
- input [4:0] ADDRH;
- input [1:0] DIA;
- input [1:0] DIB;
- input [1:0] DIC;
- input [1:0] DID;
- input [1:0] DIE;
- input [1:0] DIF;
- input [1:0] DIG;
- input [1:0] DIH;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM64M (...);
- parameter [63:0] INIT_A = 64'h0000000000000000;
- parameter [63:0] INIT_B = 64'h0000000000000000;
- parameter [63:0] INIT_C = 64'h0000000000000000;
- parameter [63:0] INIT_D = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output DOA;
- output DOB;
- output DOC;
- output DOD;
- input [5:0] ADDRA;
- input [5:0] ADDRB;
- input [5:0] ADDRC;
- input [5:0] ADDRD;
- input DIA;
- input DIB;
- input DIC;
- input DID;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM64M8 (...);
- parameter [63:0] INIT_A = 64'h0000000000000000;
- parameter [63:0] INIT_B = 64'h0000000000000000;
- parameter [63:0] INIT_C = 64'h0000000000000000;
- parameter [63:0] INIT_D = 64'h0000000000000000;
- parameter [63:0] INIT_E = 64'h0000000000000000;
- parameter [63:0] INIT_F = 64'h0000000000000000;
- parameter [63:0] INIT_G = 64'h0000000000000000;
- parameter [63:0] INIT_H = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output DOA;
- output DOB;
- output DOC;
- output DOD;
- output DOE;
- output DOF;
- output DOG;
- output DOH;
- input [5:0] ADDRA;
- input [5:0] ADDRB;
- input [5:0] ADDRC;
- input [5:0] ADDRD;
- input [5:0] ADDRE;
- input [5:0] ADDRF;
- input [5:0] ADDRG;
- input [5:0] ADDRH;
- input DIA;
- input DIB;
- input DIC;
- input DID;
- input DIE;
- input DIF;
- input DIG;
- input DIH;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module ROM16X1 (...);
- parameter [127:0] INIT = 16'h0000;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
-endmodule
-
-module ROM32X1 (...);
- parameter [31:0] INIT = 32'h00000000;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
-endmodule
-
-module ROM64X1 (...);
- parameter [63:0] INIT = 64'h0000000000000000;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
-endmodule
-
-module ROM128X1 (...);
- parameter [127:0] INIT = 128'h00000000000000000000000000000000;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input A6;
-endmodule
-
-module ROM256X1 (...);
- parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input A6;
- input A7;
-endmodule
-
module FDCPE (...);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 3d4a65c5d..2c5686a35 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -282,6 +282,7 @@ struct SynthXilinxPass : public ScriptPass
void script() YS_OVERRIDE
{
+ bool do_iopad = iopad || (ise && !noiopad);
std::string ff_map_file;
if (help_mode)
ff_map_file = "+/xilinx/{family}_ff_map.v";
@@ -305,6 +306,8 @@ struct SynthXilinxPass : public ScriptPass
run("proc");
if (flatten || help_mode)
run("flatten", "(with '-flatten')");
+ run("tribuf -logic");
+ run("deminout");
run("opt_expr");
run("opt_clean");
run("check");
@@ -503,6 +506,9 @@ struct SynthXilinxPass : public ScriptPass
}
if (check_label("map_cells")) {
+ // Needs to be done before logic optimization, so that inverters (OE vs T) are handled.
+ if (help_mode || do_iopad)
+ run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I -toutpad $__XILINX_TOUTPAD OE:I:O -tinoutpad $__XILINX_TINOUTPAD OE:O:I:IO A:top", "(only if '-iopad' or '-ise' and not '-noiopad')");
std::string techmap_args = "-map +/techmap.v -map +/xilinx/cells_map.v";
if (widemux > 0)
techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
@@ -561,15 +567,8 @@ struct SynthXilinxPass : public ScriptPass
}
if (check_label("finalize")) {
- bool do_iopad = iopad || (ise && !noiopad);
- if (help_mode || !noclkbuf) {
- if (help_mode || do_iopad)
- run("clkbufmap -buf BUFG O:I -inpad IBUFG O:I", "(skip if '-noclkbuf', '-inpad' passed if '-iopad' or '-ise' and not '-noiopad')");
- else
- run("clkbufmap -buf BUFG O:I");
- }
- if (help_mode || do_iopad)
- run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopad' or '-ise' and not '-noiopad')");
+ if (help_mode || !noclkbuf)
+ run("clkbufmap -buf BUFG O:I ", "(skip if '-noclkbuf')");
if (help_mode || ise)
run("extractinv -inv INV O:I", "(only if '-ise')");
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-18 00:14:48 +0000