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-rw-r--r--techlibs/xilinx/abc9_map.v135
-rw-r--r--techlibs/xilinx/abc9_model.v7
-rw-r--r--techlibs/xilinx/abc9_unmap.v7
-rw-r--r--techlibs/xilinx/abc9_xc7.box51
-rw-r--r--techlibs/xilinx/cells_sim.v294
-rw-r--r--techlibs/xilinx/synth_xilinx.cc4
6 files changed, 449 insertions, 49 deletions
diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 0eac08f3f..0b81be15f 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -18,8 +18,143 @@
*
*/
+// The following techmapping rules are intended to be run (with -max_iter 1)
+// before invoking the `abc9` pass in order to transform the design into
+// a format that it understands.
+//
+// For example, (complex) flip-flops are expected to be described as an
+// combinatorial box (containing all control logic such as clock enable
+// or synchronous resets) followed by a basic D-Q flop.
+
// ============================================================================
+// The purpose of the following FD* rules are to wrap the flop (which, when
+// called with the `_ABC' macro set captures only its combinatorial
+// behaviour) with:
+// (a) a special $__ABC_FF_ in front of the FD*'s output, indicating to abc9
+// the connectivity of its basic D-Q flop
+// (b) a special TECHMAP_REPLACE_.$currQ wire that will be used for feedback
+// into the (combinatorial) FD* cell to facilitate clock-enable behaviour
+module FDRE (output reg Q, input C, CE, D, R);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_R_INVERTED = 1'b0;
+ wire $nextQ;
+ FDRE #(
+ .INIT(INIT),
+ .IS_C_INVERTED(IS_C_INVERTED),
+ .IS_D_INVERTED(IS_D_INVERTED),
+ .IS_R_INVERTED(IS_R_INVERTED)
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
+ );
+ wire _TECHMAP_REPLACE_.$currQ = Q;
+ \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q));
+endmodule
+module FDRE_1 (output reg Q, input C, CE, D, R);
+ parameter [0:0] INIT = 1'b0;
+ wire $nextQ;
+ FDRE_1 #(
+ .INIT(|0),
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
+ );
+ wire _TECHMAP_REPLACE_.$currQ = Q;
+ \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q));
+endmodule
+
+module FDCE (output reg Q, input C, CE, D, CLR);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_CLR_INVERTED = 1'b0;
+ wire $currQ, $nextQ;
+ FDCE #(
+ .INIT(INIT),
+ .IS_C_INVERTED(IS_C_INVERTED),
+ .IS_D_INVERTED(IS_D_INVERTED),
+ .IS_CLR_INVERTED(IS_CLR_INVERTED)
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
+ );
+ wire _TECHMAP_REPLACE_.$currQ = Q;
+ \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ));
+ \$__ABC_ASYNC abc_async (.A($currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
+endmodule
+module FDCE_1 (output reg Q, input C, CE, D, CLR);
+ parameter [0:0] INIT = 1'b0;
+ wire $nextQ, $currQ;
+ FDCE_1 #(
+ .INIT(INIT)
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
+ );
+ wire _TECHMAP_REPLACE_.$currQ = Q;
+ \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ));
+ \$__ABC_ASYNC abc_async (.A($currQ), .S(CLR), .Y(Q));
+endmodule
+
+module FDPE (output reg Q, input C, CE, D, PRE);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_PRE_INVERTED = 1'b0;
+ wire $nextQ, $currQ;
+ FDPE #(
+ .INIT(INIT),
+ .IS_C_INVERTED(IS_C_INVERTED),
+ .IS_D_INVERTED(IS_D_INVERTED),
+ .IS_PRE_INVERTED(IS_PRE_INVERTED),
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
+ );
+ wire _TECHMAP_REPLACE_.$currQ = Q;
+ \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ));
+ \$__ABC_ASYNC abc_async (.A($currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
+endmodule
+module FDPE_1 (output reg Q, input C, CE, D, PRE);
+ parameter [0:0] INIT = 1'b0;
+ wire $nextQ, $currQ;
+ FDPE_1 #(
+ .INIT(INIT)
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
+ );
+ wire _TECHMAP_REPLACE_.$currQ = Q;
+ \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ));
+ \$__ABC_ASYNC abc_async (.A($currQ), .S(PRE), .Y(Q));
+endmodule
+
+module FDSE (output reg Q, input C, CE, D, S);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_S_INVERTED = 1'b0;
+ wire $nextQ;
+ FDSE #(
+ .INIT(INIT),
+ .IS_C_INVERTED(IS_C_INVERTED),
+ .IS_D_INVERTED(IS_D_INVERTED),
+ .IS_S_INVERTED(IS_S_INVERTED)
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
+ );
+ wire _TECHMAP_REPLACE_.$currQ = Q;
+ \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q));
+endmodule
+module FDSE_1 (output reg Q, input C, CE, D, S);
+ parameter [0:0] INIT = 1'b0;
+ wire $nextQ;
+ FDSE_1 #(
+ .INIT(|0),
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
+ );
+ wire _TECHMAP_REPLACE_.$currQ = Q;
+ \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q));
+endmodule
+
module RAM32X1D (
output DPO, SPO,
(* techmap_autopurge *) input D,
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v
index 8c8e1556c..74b5cf66a 100644
--- a/techlibs/xilinx/abc9_model.v
+++ b/techlibs/xilinx/abc9_model.v
@@ -30,6 +30,13 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
: (S0 ? I1 : I0);
endmodule
+module \$__ABC_FF_ (input D, output Q);
+endmodule
+
+(* abc_box_id = 1000 *)
+module \$__ABC_ASYNC (input A, S, output Y);
+endmodule
+
// Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
// Necessary since RAMD* and SRL* have both combinatorial (i.e.
// same-cycle read operation) and sequential (write operation
diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v
index ad6469702..f97b0bc66 100644
--- a/techlibs/xilinx/abc9_unmap.v
+++ b/techlibs/xilinx/abc9_unmap.v
@@ -20,6 +20,13 @@
// ============================================================================
+module \$__ABC9_ASYNC (input A, S, output Y);
+ assign Y = A;
+endmodule
+
+module \$__ABC9_FF_ (input D, output Q);
+ assign Q = D;
+
module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
assign Y = A;
endmodule
diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box
index 774388d49..6814b101f 100644
--- a/techlibs/xilinx/abc9_xc7.box
+++ b/techlibs/xilinx/abc9_xc7.box
@@ -41,6 +41,57 @@ CARRY4 4 1 10 8
592 540 520 356 - 512 548 292 - 228
580 526 507 398 385 508 528 378 380 114
+# Box to emulate async behaviour of FD[CP]*
+# Inputs: A S
+# Outputs: Y
+$__ABC_ASYNC 1000 0 2 1
+0 764
+
+# The following FD*.{CE,R,CLR,PRE) are offset by 46ps to
+# reflect the -46ps Tsu
+# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
+# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
+
+# Inputs: C CE D R \$currQ
+# Outputs: Q
+FDRE 1001 1 5 1
+0 151 0 446 0
+
+# Inputs: C CE D R \$currQ
+# Outputs: Q
+FDRE_1 1002 1 5 1
+0 151 0 446 0
+
+# Inputs: C CE CLR D \$currQ
+# Outputs: Q
+FDCE 1003 1 5 1
+0 151 806 0 0
+
+# Inputs: C CE CLR D \$currQ
+# Outputs: Q
+FDCE_1 1004 1 5 1
+0 151 806 0 0
+
+# Inputs: C CE D PRE \$currQ
+# Outputs: Q
+FDPE 1005 1 5 1
+0 151 0 806 0
+
+# Inputs: C CE D PRE \$currQ
+# Outputs: Q
+FDPE_1 1006 1 5 1
+0 151 0 806 0
+
+# Inputs: C CE D S \$currQ
+# Outputs: Q
+FDSE 1007 1 5 1
+0 151 0 446 0
+
+# Inputs: C CE D S \$currQ
+# Outputs: Q
+FDSE_1 1008 1 5 1
+0 151 0 446 0
+
# SLICEM/A6LUT
# Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
# Necessary since RAMD* and SRL* have both combinatorial (i.e.
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 28cd208cd..309ee500a 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -240,6 +240,7 @@ endmodule
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
+(* abc9_box_id=1001, lib_whitebox, abc9_flop *)
module FDRE (
(* abc9_arrival=303 *)
output reg Q,
@@ -257,35 +258,72 @@ module FDRE (
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0;
initial Q <= INIT;
+ wire \$currQ ;
+ reg \$nextQ ;
+ always @* if (R == !IS_R_INVERTED) \$nextQ = 1'b0; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
+`ifdef _ABC9
+ // `abc9' requires that complex flops be split into a combinatorial
+ // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `$currQ' wire.
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
+ // Special signal indicating control domain
+ // (which, combined with this spell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] $abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
+ always @* Q = \$nextQ ;
+`else
+ assign \$currQ = Q;
generate case (|IS_C_INVERTED)
- 1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
- 1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+ 1'b0: always @(posedge C) Q <= \$nextQ ;
+ 1'b1: always @(negedge C) Q <= \$nextQ ;
endcase endgenerate
+`endif
endmodule
-module FDSE (
+(* abc9_box_id=1002, lib_whitebox, abc9_flop *)
+module FDRE_1 (
(* abc9_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
- (* invertible_pin = "IS_C_INVERTED" *)
input C,
- input CE,
- (* invertible_pin = "IS_D_INVERTED" *)
- input D,
- (* invertible_pin = "IS_S_INVERTED" *)
- input S
+ input CE, D, R
);
- parameter [0:0] INIT = 1'b1;
- parameter [0:0] IS_C_INVERTED = 1'b0;
- parameter [0:0] IS_D_INVERTED = 1'b0;
- parameter [0:0] IS_S_INVERTED = 1'b0;
+ parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
- generate case (|IS_C_INVERTED)
- 1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
- 1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
- endcase endgenerate
+ wire \$currQ ;
+ reg \$nextQ ;
+ always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else \$nextQ = \$currQ ;
+`ifdef _ABC9
+ // `abc9' requires that complex flops be split into a combinatorial
+ // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `$currQ' wire.
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+ // Special signal indicating control domain
+ // (which, combined with this spell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
+ always @* Q = \$nextQ ;
+`else
+ assign \$currQ = Q;
+ always @(negedge C) Q <= \$nextQ ;
+`endif
endmodule
+(* abc9_box_id=1003, lib_whitebox, abc9_flop *)
module FDCE (
(* abc9_arrival=303 *)
output reg Q,
@@ -303,14 +341,78 @@ module FDCE (
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
initial Q <= INIT;
+ wire \$currQ ;
+ reg \$nextQ ;
+ always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
+`ifdef _ABC9
+ // `abc9' requires that complex flops be split into a combinatorial
+ // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `$currQ' wire.
+ // Since this is an async flop, async behaviour is also dealt with
+ // using the $_ABC9_ASYNC box by abc9_map.v
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
+ // Special signal indicating control domain
+ // (which, combined with this spell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] $abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
+ always @* Q = \$nextQ ;
+`else
+ assign \$currQ = Q;
generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
- 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
- 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
- 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
- 2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+ 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
+ 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
+ 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
+ 2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
endcase endgenerate
+`endif
endmodule
+(* abc9_box_id=1004, lib_whitebox, abc9_flop *)
+module FDCE_1 (
+ (* abc9_arrival=303 *)
+ output reg Q,
+ (* clkbuf_sink *)
+ input C,
+ input CE, D, CLR
+);
+ parameter [0:0] INIT = 1'b0;
+ initial Q <= INIT;
+ wire \$currQ ;
+ reg \$nextQ ;
+ always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
+`ifdef _ABC9
+ // `abc9' requires that complex flops be split into a combinatorial
+ // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `$currQ' wire.
+ // Since this is an async flop, async behaviour is also dealt with
+ // using the $_ABC9_ASYNC box by abc9_map.v
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+ // Special signal indicating control domain
+ // (which, combined with this spell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
+ always @* Q = \$nextQ ;
+`else
+ assign \$currQ = Q;
+ always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= \$nextQ ;
+`endif
+endmodule
+
+(* abc9_box_id=1005, lib_whitebox, abc9_flop *)
module FDPE (
(* abc9_arrival=303 *)
output reg Q,
@@ -328,60 +430,158 @@ module FDPE (
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
initial Q <= INIT;
+ wire \$currQ ;
+ reg \$nextQ ;
+ always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
+`ifdef _ABC9
+ // `abc9' requires that complex flops be split into a combinatorial
+ // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `$currQ' wire.
+ // Since this is an async flop, async behaviour is also dealt with
+ // using the $_ABC9_ASYNC box by abc9_map.v
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
+ // Special signal indicating control domain
+ // (which, combined with this spell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] $abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
+ always @* Q = \$nextQ ;
+`else
+ assign \$currQ = Q;
generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
- 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
- 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
- 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
- 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+ 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
+ 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
+ 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
+ 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
endcase endgenerate
+`endif
endmodule
-module FDRE_1 (
- (* abc9_arrival=303 *)
- output reg Q,
- (* clkbuf_sink *)
- input C,
- input CE, D, R
-);
- parameter [0:0] INIT = 1'b0;
- initial Q <= INIT;
- always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
-endmodule
-
-module FDSE_1 (
+(* abc9_box_id=1006, lib_whitebox, abc9_flop *)
+module FDPE_1 (
(* abc9_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
input C,
- input CE, D, S
+ input CE, D, PRE
);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
- always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
+ wire \$currQ ;
+ reg \$nextQ ;
+ always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
+`ifdef _ABC9
+ // `abc9' requires that complex flops be split into a combinatorial
+ // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `$currQ' wire.
+ // Since this is an async flop, async behaviour is also dealt with
+ // using the $_ABC9_ASYNC box by abc9_map.v
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+ // Special signal indicating control domain
+ // (which, combined with this spell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
+ always @* Q = \$nextQ ;
+`else
+ assign \$currQ = Q;
+ always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= \$nextQ ;
+`endif
endmodule
-module FDCE_1 (
+(* abc9_box_id=1007, lib_whitebox, abc9_flop *)
+module FDSE (
(* abc9_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
input C,
- input CE, D, CLR
+ input CE,
+ (* invertible_pin = "IS_D_INVERTED" *)
+ input D,
+ (* invertible_pin = "IS_S_INVERTED" *)
+ input S
);
- parameter [0:0] INIT = 1'b0;
+ parameter [0:0] INIT = 1'b1;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_S_INVERTED = 1'b0;
initial Q <= INIT;
- always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
+ wire \$currQ ;
+ reg \$nextQ ;
+ always @* if (S == !IS_S_INVERTED) \$nextQ = 1'b1; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
+`ifdef _ABC9
+ // `abc9' requires that complex flops be split into a combinatorial
+ // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `$currQ' wire.
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
+ // Special signal indicating control domain
+ // (which, combined with this spell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] $abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
+ always @* Q = \$nextQ ;
+`else
+ assign \$currQ = Q;
+ generate case (|IS_C_INVERTED)
+ 1'b0: always @(posedge C) Q <= \$nextQ ;
+ 1'b1: always @(negedge C) Q <= \$nextQ ;
+ endcase endgenerate
+`endif
endmodule
-module FDPE_1 (
+(* abc9_box_id=1008, lib_whitebox, abc9_flop *)
+module FDSE_1 (
(* abc9_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
input C,
- input CE, D, PRE
+ input CE, D, S
);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
- always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
+ wire \$currQ ;
+ reg \$nextQ ;
+ always @* if (S) \$nextQ = 1'b1; else if (CE) \$nextQ = D; else \$nextQ = \$currQ ;
+`ifdef _ABC9
+ // `abc9' requires that complex flops be split into a combinatorial
+ // box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
+ // In order to achieve clock-enable behaviour, the current value
+ // of the sequential output is required which Yosys will
+ // connect to the special `$currQ' wire.
+
+ // Special signal indicating clock domain
+ // (used to partition the module so that `abc9' only performs
+ // sequential synthesis (reachability analysis) correctly on
+ // one domain at a time)
+ wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+ // Special signal indicating control domain
+ // (which, combined with this spell type, encodes to `abc9'
+ // which flops may be merged together)
+ wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
+ always @* Q = \$nextQ ;
+`else
+ assign \$currQ = Q;
+ always @(negedge C) Q <= \$nextQ ;
+`endif
endmodule
module LDCE (
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 5c2b1402c..16b607aac 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -284,9 +284,9 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("begin")) {
if (vpr)
- run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
+ run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
else
- run("read_verilog -lib +/xilinx/cells_sim.v");
+ run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v");
if (help_mode)
run("read_verilog -lib +/xilinx/{family}_cells_xtra.v");
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 22:44:52 +0000