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-rw-r--r--techlibs/xilinx/Makefile.inc1
-rw-r--r--techlibs/xilinx/cells_map.v120
-rw-r--r--techlibs/xilinx/mux_map.v52
-rw-r--r--techlibs/xilinx/synth_xilinx.cc24
4 files changed, 3 insertions, 194 deletions
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 2f3945167..296edace9 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -30,7 +30,6 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.box))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.lut))
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index f8f9356bc..6b92d2ea9 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -142,123 +142,3 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
end
endgenerate
endmodule
-
-module \$__XILINX_SHIFTX (A, B, Y);
- parameter A_SIGNED = 0;
- parameter B_SIGNED = 0;
- parameter A_WIDTH = 1;
- parameter B_WIDTH = 1;
- parameter Y_WIDTH = 1;
-
- input [A_WIDTH-1:0] A;
- input [B_WIDTH-1:0] B;
- output [Y_WIDTH-1:0] Y;
-
- parameter [A_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;
- parameter [A_WIDTH-1:0] _TECHMAP_CONSTVAL_A_ = 0;
- parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
- parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
-
- function integer compute_num_leading_X_in_A;
- integer i, c;
- begin
- compute_num_leading_X_in_A = 0;
- c = 1;
- for (i = A_WIDTH-1; i >= 0; i=i-1) begin
- if (!_TECHMAP_CONSTMSK_A_[i] || _TECHMAP_CONSTVAL_A_[i] !== 1'bx)
- c = 0;
- compute_num_leading_X_in_A = compute_num_leading_X_in_A + c;
- end
- end
- endfunction
- localparam num_leading_X_in_A = compute_num_leading_X_in_A();
-
- generate
- genvar i, j;
- // Bit-blast
- if (Y_WIDTH > 1) begin
- for (i = 0; i < Y_WIDTH; i++)
- \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));
- end
- // If the LSB of B is constant zero (and Y_WIDTH is 1) then
- // we can optimise by removing every other entry from A
- // and popping the constant zero from B
- else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin
- wire [(A_WIDTH+1)/2-1:0] A_i;
- for (i = 0; i < (A_WIDTH+1)/2; i++)
- assign A_i[i] = A[i*2];
- \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
- end
- // Trim off any leading 1'bx -es in A, and resize B accordingly
- else if (num_leading_X_in_A > 0) begin
- localparam A_WIDTH_new = A_WIDTH - num_leading_X_in_A;
- localparam B_WIDTH_new = $clog2(A_WIDTH_new);
- \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH_new), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B[B_WIDTH_new-1:0]), .Y(Y));
- end
- else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
- \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
- end
- else if (B_WIDTH == 3) begin
- localparam a_width0 = 2 ** 2;
- localparam a_widthN = A_WIDTH - a_width0;
- wire T0, T1;
- \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[a_width0-1:0]), .B(B[2-1:0]), .Y(T0));
- if (a_widthN > 1)
- \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
- else
- assign T1 = A[A_WIDTH-1];
- MUXF7 fpga_hard_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y));
- end
- else if (B_WIDTH == 4) begin
- localparam a_width0 = 2 ** 2;
- localparam num_mux8 = A_WIDTH / a_width0;
- localparam a_widthN = A_WIDTH - num_mux8*a_width0;
- wire [4-1:0] T;
- wire T0, T1;
- for (i = 0; i < 4; i++)
- if (i < num_mux8)
- \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]), .Y(T[i]));
- else if (i == num_mux8 && a_widthN > 0) begin
- if (a_widthN > 1)
- \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
- else
- assign T[i] = A[A_WIDTH-1];
- end
- else
- assign T[i] = 1'bx;
- MUXF7 fpga_hard_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[2]), .O(T0));
- MUXF7 fpga_hard_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[2]), .O(T1));
- MUXF8 fpga_hard_mux_2 (.I0(T0), .I1(T1), .S(B[3]), .O(Y));
- end
- else begin
- localparam a_width0 = 2 ** 4;
- localparam num_mux16 = A_WIDTH / a_width0;
- localparam a_widthN = A_WIDTH - num_mux16*a_width0;
- wire [(2**(B_WIDTH-4))-1:0] T;
- for (i = 0; i < 2 ** (B_WIDTH-4); i++)
- if (i < num_mux16)
- \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i]));
- else if (i == num_mux16 && a_widthN > 0) begin
- if (a_widthN > 1)
- \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
- else
- assign T[i] = A[A_WIDTH-1];
- end
- else
- assign T[i] = 1'bx;
- \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
- end
- endgenerate
-endmodule
-
-module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
-input A, B, C, D, E, F, G, H, S, T, U;
-output Y;
- \$__XILINX_SHIFTX #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({H,G,F,E,D,C,B,A}), .B({U,T,S}), .Y(Y));
-endmodule
-
-module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);
-input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
-output Y;
- \$__XILINX_SHIFTX #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y));
-endmodule
diff --git a/techlibs/xilinx/mux_map.v b/techlibs/xilinx/mux_map.v
deleted file mode 100644
index 0fa8db736..000000000
--- a/techlibs/xilinx/mux_map.v
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- * 2019 Eddie Hung <eddie@fpgeh.com>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-module \$shiftx (A, B, Y);
- parameter A_SIGNED = 0;
- parameter B_SIGNED = 0;
- parameter A_WIDTH = 1;
- parameter B_WIDTH = 1;
- parameter Y_WIDTH = 1;
-
- input [A_WIDTH-1:0] A;
- input [B_WIDTH-1:0] B;
- output [Y_WIDTH-1:0] Y;
-
- parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
- parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
-
- generate
- genvar i, j;
- // TODO: Check if this opt still necessary
- if (B_SIGNED) begin
- if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
- // Optimisation to remove B_SIGNED if sign bit of B is constant-0
- \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
- else
- wire _TECHMAP_FAIL_ = 1;
- end
- else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
- wire _TECHMAP_FAIL_ = 1;
- end
- else begin
- \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
- end
- endgenerate
-endmodule
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index f966115cd..42a3bba12 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -70,9 +70,6 @@ struct SynthXilinxPass : public ScriptPass
log(" -nosrl\n");
log(" disable inference of shift registers\n");
log("\n");
- log(" -nomux\n");
- log(" disable inference of wide multiplexers\n");
- log("\n");
log(" -run <from_label>:<to_label>\n");
log(" only run the commands between the labels (see below). an empty\n");
log(" from label is synonymous to 'begin', and empty to label is\n");
@@ -94,7 +91,7 @@ struct SynthXilinxPass : public ScriptPass
}
std::string top_opt, edif_file, blif_file, abc, arch;
- bool flatten, retime, vpr, nocarry, nobram, nodram, nosrl, nomux;
+ bool flatten, retime, vpr, nocarry, nobram, nodram, nosrl;
void clear_flags() YS_OVERRIDE
{
@@ -109,7 +106,6 @@ struct SynthXilinxPass : public ScriptPass
nobram = false;
nodram = false;
nosrl = false;
- nomux = false;
arch = "xc7";
}
@@ -173,10 +169,6 @@ struct SynthXilinxPass : public ScriptPass
nosrl = true;
continue;
}
- if (args[argidx] == "-nomux") {
- nomux = true;
- continue;
- }
if (args[argidx] == "-abc9") {
abc = "abc9";
continue;
@@ -225,15 +217,11 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("coarse")) {
run("synth -run coarse");
- //if (!nomux || help_mode)
- // run("muxpack", "(skip if '-nomux')");
-
// shregmap -tech xilinx can cope with $shiftx and $mux
// cells for identifying variable-length shift registers,
// so attempt to convert $pmux-es to the former
- // Also: wide multiplexer inference benefits from this too
- if (!(nosrl && nomux) || help_mode)
- run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')");
+ if (!nosrl || help_mode)
+ run("pmux2shiftx", "(skip if '-nosrl')");
// Run a number of peephole optimisations, including one
// that optimises $mul cells driving $shiftx's B input
@@ -272,10 +260,6 @@ struct SynthXilinxPass : public ScriptPass
std::string techmap_files = " -map +/techmap.v";
if (help_mode)
- techmap_files += " [-map +/xilinx/mux_map.v]";
- else if (!nomux)
- techmap_files += " -map +/xilinx/mux_map.v";
- if (help_mode)
techmap_files += " [-map +/xilinx/arith_map.v]";
else if (!nocarry) {
techmap_files += " -map +/xilinx/arith_map.v";
@@ -289,8 +273,6 @@ struct SynthXilinxPass : public ScriptPass
}
if (check_label("map_cells")) {
- if (!nomux || help_mode)
- run("muxcover -mux8 -mux16", "(skip if '-nomux')");
run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
run("clean");
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 01:50:57 +0000