diff options
Diffstat (limited to 'techlibs')
-rw-r--r-- | techlibs/xilinx/cells_sim.v | 44 | ||||
-rw-r--r-- | techlibs/xilinx/cells_xtra.py | 4 | ||||
-rw-r--r-- | techlibs/xilinx/xc6s_cells_xtra.v | 30 | ||||
-rw-r--r-- | techlibs/xilinx/xc6v_cells_xtra.v | 30 | ||||
-rw-r--r-- | techlibs/xilinx/xc7_cells_xtra.v | 30 | ||||
-rw-r--r-- | techlibs/xilinx/xcu_cells_xtra.v | 30 |
6 files changed, 46 insertions, 122 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 0b6341938..258999f18 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -384,6 +384,50 @@ module FDPE_1 ( always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule +module LDCE ( + output reg Q, + (* invertible_pin = "IS_CLR_INVERTED" *) + input CLR, + input D, + (* invertible_pin = "IS_G_INVERTED" *) + input G, + input GE +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_CLR_INVERTED = 1'b0; + parameter [0:0] IS_G_INVERTED = 1'b0; + parameter MSGON = "TRUE"; + parameter XON = "TRUE"; + initial Q = INIT; + wire clr = CLR ^ IS_CLR_INVERTED; + wire g = G ^ IS_G_INVERTED; + always @* + if (clr) Q = 1'b0; + else if (GE && g) Q = D; +endmodule + +module LDPE ( + output reg Q, + input D, + (* invertible_pin = "IS_G_INVERTED" *) + input G, + input GE, + (* invertible_pin = "IS_PRE_INVERTED" *) + input PRE +); + parameter [0:0] INIT = 1'b1; + parameter [0:0] IS_G_INVERTED = 1'b0; + parameter [0:0] IS_PRE_INVERTED = 1'b0; + parameter MSGON = "TRUE"; + parameter XON = "TRUE"; + initial Q = INIT; + wire g = G ^ IS_G_INVERTED; + wire pre = PRE ^ IS_PRE_INVERTED; + always @* + if (pre) Q = 1'b1; + else if (GE && g) Q = D; +endmodule + module RAM32X1D ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 (* abc_arrival=1153 *) diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index 561a61943..13dbc0e14 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -108,8 +108,8 @@ XC6S_CELLS = [ # Cell('FDRE'), # Cell('FDSE'), Cell('IDDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}), - Cell('LDCE'), - Cell('LDPE'), + # Cell('LDCE'), + # Cell('LDPE'), Cell('ODDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}), # Slice/CLB primitives. diff --git a/techlibs/xilinx/xc6s_cells_xtra.v b/techlibs/xilinx/xc6s_cells_xtra.v index 014e73df0..f8dcce81d 100644 --- a/techlibs/xilinx/xc6s_cells_xtra.v +++ b/techlibs/xilinx/xc6s_cells_xtra.v @@ -1793,36 +1793,6 @@ module IDDR2 (...); input S; endmodule -module LDCE (...); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_CLR_INVERTED = 1'b0; - parameter [0:0] IS_G_INVERTED = 1'b0; - parameter MSGON = "TRUE"; - parameter XON = "TRUE"; - output Q; - (* invertible_pin = "IS_CLR_INVERTED" *) - input CLR; - input D; - (* invertible_pin = "IS_G_INVERTED" *) - input G; - input GE; -endmodule - -module LDPE (...); - parameter [0:0] INIT = 1'b1; - parameter [0:0] IS_G_INVERTED = 1'b0; - parameter [0:0] IS_PRE_INVERTED = 1'b0; - parameter MSGON = "TRUE"; - parameter XON = "TRUE"; - output Q; - input D; - (* invertible_pin = "IS_G_INVERTED" *) - input G; - input GE; - (* invertible_pin = "IS_PRE_INVERTED" *) - input PRE; -endmodule - module ODDR2 (...); parameter DDR_ALIGNMENT = "NONE"; parameter [0:0] INIT = 1'b0; diff --git a/techlibs/xilinx/xc6v_cells_xtra.v b/techlibs/xilinx/xc6v_cells_xtra.v index 263bcc69d..b228e404d 100644 --- a/techlibs/xilinx/xc6v_cells_xtra.v +++ b/techlibs/xilinx/xc6v_cells_xtra.v @@ -2648,36 +2648,6 @@ module IDDR_2CLK (...); input S; endmodule -module LDCE (...); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_CLR_INVERTED = 1'b0; - parameter [0:0] IS_G_INVERTED = 1'b0; - parameter MSGON = "TRUE"; - parameter XON = "TRUE"; - output Q; - (* invertible_pin = "IS_CLR_INVERTED" *) - input CLR; - input D; - (* invertible_pin = "IS_G_INVERTED" *) - input G; - input GE; -endmodule - -module LDPE (...); - parameter [0:0] INIT = 1'b1; - parameter [0:0] IS_G_INVERTED = 1'b0; - parameter [0:0] IS_PRE_INVERTED = 1'b0; - parameter MSGON = "TRUE"; - parameter XON = "TRUE"; - output Q; - input D; - (* invertible_pin = "IS_G_INVERTED" *) - input G; - input GE; - (* invertible_pin = "IS_PRE_INVERTED" *) - input PRE; -endmodule - module ODDR (...); parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; parameter INIT = 1'b0; diff --git a/techlibs/xilinx/xc7_cells_xtra.v b/techlibs/xilinx/xc7_cells_xtra.v index 817932e9f..0d16f81c3 100644 --- a/techlibs/xilinx/xc7_cells_xtra.v +++ b/techlibs/xilinx/xc7_cells_xtra.v @@ -5149,36 +5149,6 @@ module IDDR_2CLK (...); input S; endmodule -module LDCE (...); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_CLR_INVERTED = 1'b0; - parameter [0:0] IS_G_INVERTED = 1'b0; - parameter MSGON = "TRUE"; - parameter XON = "TRUE"; - output Q; - (* invertible_pin = "IS_CLR_INVERTED" *) - input CLR; - input D; - (* invertible_pin = "IS_G_INVERTED" *) - input G; - input GE; -endmodule - -module LDPE (...); - parameter [0:0] INIT = 1'b1; - parameter [0:0] IS_G_INVERTED = 1'b0; - parameter [0:0] IS_PRE_INVERTED = 1'b0; - parameter MSGON = "TRUE"; - parameter XON = "TRUE"; - output Q; - input D; - (* invertible_pin = "IS_G_INVERTED" *) - input G; - input GE; - (* invertible_pin = "IS_PRE_INVERTED" *) - input PRE; -endmodule - module ODDR (...); parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; parameter INIT = 1'b0; diff --git a/techlibs/xilinx/xcu_cells_xtra.v b/techlibs/xilinx/xcu_cells_xtra.v index 2d331a221..4523b5210 100644 --- a/techlibs/xilinx/xcu_cells_xtra.v +++ b/techlibs/xilinx/xcu_cells_xtra.v @@ -10731,36 +10731,6 @@ module IDDRE1 (...); input R; endmodule -module LDCE (...); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_CLR_INVERTED = 1'b0; - parameter [0:0] IS_G_INVERTED = 1'b0; - parameter MSGON = "TRUE"; - parameter XON = "TRUE"; - output Q; - (* invertible_pin = "IS_CLR_INVERTED" *) - input CLR; - input D; - (* invertible_pin = "IS_G_INVERTED" *) - input G; - input GE; -endmodule - -module LDPE (...); - parameter [0:0] INIT = 1'b1; - parameter [0:0] IS_G_INVERTED = 1'b0; - parameter [0:0] IS_PRE_INVERTED = 1'b0; - parameter MSGON = "TRUE"; - parameter XON = "TRUE"; - output Q; - input D; - (* invertible_pin = "IS_G_INVERTED" *) - input G; - input GE; - (* invertible_pin = "IS_PRE_INVERTED" *) - input PRE; -endmodule - module ODDRE1 (...); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D1_INVERTED = 1'b0; |