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-rw-r--r--techlibs/xilinx/Makefile.inc3
-rw-r--r--techlibs/xilinx/abc_map.v123
-rw-r--r--techlibs/xilinx/abc_model.v34
-rw-r--r--techlibs/xilinx/abc_unmap.v28
-rw-r--r--techlibs/xilinx/abc_xc7.box39
-rw-r--r--techlibs/xilinx/cells_map.v2
-rw-r--r--techlibs/xilinx/cells_sim.v96
-rw-r--r--techlibs/xilinx/synth_xilinx.cc21
-rw-r--r--techlibs/xilinx/xc7_brams_bb.v10
9 files changed, 301 insertions, 55 deletions
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 2b1af289c..2efcf7d90 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -39,6 +39,9 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_map.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_unmap.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_model.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7_nowide.lut))
diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
new file mode 100644
index 000000000..0c85d6656
--- /dev/null
+++ b/techlibs/xilinx/abc_map.v
@@ -0,0 +1,123 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * 2019 Eddie Hung <eddie@fpgeh.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// ============================================================================
+
+module RAM32X1D (
+ output DPO, SPO,
+ input D,
+ input WCLK,
+ input WE,
+ input A0, A1, A2, A3, A4,
+ input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
+);
+ parameter INIT = 32'h0;
+ parameter IS_WCLK_INVERTED = 1'b0;
+ wire \$DPO , \$SPO ;
+ RAM32X1D #(
+ .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
+ ) _TECHMAP_REPLACE_ (
+ .DPO(\$DPO ), .SPO(\$SPO ),
+ .D(D), .WCLK(WCLK), .WE(WE),
+ .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
+ .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
+ );
+ \$__ABC_LUT6 dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO));
+ \$__ABC_LUT6 spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO));
+endmodule
+
+module RAM64X1D (
+ output DPO, SPO,
+ input D,
+ input WCLK,
+ input WE,
+ input A0, A1, A2, A3, A4, A5,
+ input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
+);
+ parameter INIT = 64'h0;
+ parameter IS_WCLK_INVERTED = 1'b0;
+ wire \$DPO , \$SPO ;
+ RAM64X1D #(
+ .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
+ ) _TECHMAP_REPLACE_ (
+ .DPO(\$DPO ), .SPO(\$SPO ),
+ .D(D), .WCLK(WCLK), .WE(WE),
+ .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
+ .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
+ );
+ \$__ABC_LUT6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO));
+ \$__ABC_LUT6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO));
+endmodule
+
+module RAM128X1D (
+ output DPO, SPO,
+ input D,
+ input WCLK,
+ input WE,
+ input [6:0] A, DPRA
+);
+ parameter INIT = 128'h0;
+ parameter IS_WCLK_INVERTED = 1'b0;
+ wire \$DPO , \$SPO ;
+ RAM128X1D #(
+ .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
+ ) _TECHMAP_REPLACE_ (
+ .DPO(\$DPO ), .SPO(\$SPO ),
+ .D(D), .WCLK(WCLK), .WE(WE),
+ .A(A),
+ .DPRA(DPRA)
+ );
+ \$__ABC_LUT7 dpo (.A(\$DPO ), .S(A), .Y(DPO));
+ \$__ABC_LUT7 spo (.A(\$SPO ), .S(A), .Y(SPO));
+endmodule
+
+module SRL16E (
+ output Q,
+ input A0, A1, A2, A3, CE, CLK, D
+);
+ parameter [15:0] INIT = 16'h0000;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ wire \$Q ;
+ SRL16E #(
+ .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
+ ) _TECHMAP_REPLACE_ (
+ .Q(\$Q ),
+ .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
+ );
+ \$__ABC_LUT6 q (.A(\$Q ), .S({1'b1, A0, A1, A2, A3, 1'b1}), .Y(Q));
+endmodule
+
+module SRLC32E (
+ output Q,
+ output Q31,
+ input [4:0] A,
+ input CE, CLK, D
+);
+ parameter [31:0] INIT = 32'h00000000;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ wire \$Q ;
+ SRLC32E #(
+ .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
+ ) _TECHMAP_REPLACE_ (
+ .Q(\$Q ), .Q31(Q31),
+ .A(A), .CE(CE), .CLK(CLK), .D(D)
+ );
+ \$__ABC_LUT6 q (.A(\$Q ), .S({1'b1, A}), .Y(Q));
+endmodule
diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v
new file mode 100644
index 000000000..655b993f6
--- /dev/null
+++ b/techlibs/xilinx/abc_model.v
@@ -0,0 +1,34 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * 2019 Eddie Hung <eddie@fpgeh.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// ============================================================================
+
+(* abc_box_id = 3, lib_whitebox *)
+module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
+ assign O = S1 ? (S0 ? I3 : I2)
+ : (S0 ? I1 : I0);
+endmodule
+
+(* abc_box_id=2000 *)
+module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
+endmodule
+(* abc_box_id=2001 *)
+module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
+endmodule
diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v
new file mode 100644
index 000000000..f101a22d0
--- /dev/null
+++ b/techlibs/xilinx/abc_unmap.v
@@ -0,0 +1,28 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * 2019 Eddie Hung <eddie@fpgeh.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// ============================================================================
+
+module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
+ assign Y = A;
+endmodule
+module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
+ assign Y = A;
+endmodule
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 3789ff350..20da3b8a0 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -1,4 +1,5 @@
# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
+# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf
# NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out)
@@ -14,6 +15,10 @@ F7MUX 1 1 3 1
MUXF8 2 1 3 1
104 94 273
+# Box containing MUXF7.[AB] + MUXF8,
+# Necessary to make these an atomic unit so that
+# ABC cannot optimise just one of the MUXF7 away
+# and expect to save on its delay
# Inputs: I0 I1 I2 I3 S0 S1
# Outputs: O
$__MUXF78 3 1 6 1
@@ -37,22 +42,20 @@ CARRY4 4 1 10 8
580 526 507 398 385 508 528 378 380 114
# SLICEM/A6LUT
-# Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE
+# Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
+# Necessary since RAMD* and SRL* have both combinatorial (i.e.
+# same-cycle read operation) and sequential (write operation
+# is only committed on the next clock edge).
+# To model the combinatorial path, such cells have to be split
+# into comb and seq parts, with this box modelling only the former.
+# Inputs: A S0 S1 S2 S3 S4 S5
+# Outputs: Y
+$__ABC_LUT6 2000 0 7 1
+0 642 631 472 407 238 127
+
+# SLICEM/A6LUT + F7BMUX
+# Box to emulate comb/seq behaviour of RAMD128
+# Inputs: A S0 S1 S2 S3 S4 S5 S6
# Outputs: DPO SPO
-RAM32X1D 5 0 13 2
-- - - - - - 631 472 407 238 127 - -
-631 472 407 238 127 - - - - - - - -
-
-# SLICEM/A6LUT
-# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
-# Outputs: DPO SPO
-RAM64X1D 6 0 15 2
-- - - - - - - 642 631 472 407 238 127 - -
-642 631 472 407 238 127 - - - - - - - - -
-
-# SLICEM/A6LUT + F7[AB]MUX
-# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
-# Outputs: DPO SPO
-RAM128X1D 7 0 17 2
-- - - - - - - - 1009 998 839 774 605 494 450 - -
-1047 1036 877 812 643 532 478 - - - - - - - - - -
+$__ABC_LUT7 2001 0 8 1
+0 1047 1036 877 812 643 532 478
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index b8e5bafc7..a15884ec4 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -331,7 +331,6 @@ module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y)
endmodule
`endif
-`ifndef _ABC
module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
output O;
input I0, I1, I2, I3, S0, S1;
@@ -364,4 +363,3 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
else
MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
endmodule
-`endif
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index e12b77c02..6e8729256 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -184,14 +184,6 @@ module MUXF8(output O, input I0, I1, S);
assign O = S ? I1 : I0;
endmodule
-`ifdef _ABC
-(* abc_box_id = 3, lib_whitebox *)
-module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
- assign O = S1 ? (S0 ? I3 : I2)
- : (S0 ? I1 : I0);
-endmodule
-`endif
-
module XORCY(output O, input CI, LI);
assign O = CI ^ LI;
endmodule
@@ -236,7 +228,15 @@ endmodule
`endif
-module FDRE (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
+// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
+
+module FDRE (
+ (* abc_arrival=303 *)
+ output reg Q,
+ (* clkbuf_sink *)
+ input C,
+ input CE, D, R
+);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -248,7 +248,13 @@ module FDRE (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
endcase endgenerate
endmodule
-module FDSE (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
+module FDSE (
+ (* abc_arrival=303 *)
+ output reg Q,
+ (* clkbuf_sink *)
+ input C,
+ input CE, D, S
+);
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -260,7 +266,13 @@ module FDSE (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
endcase endgenerate
endmodule
-module FDCE (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
+module FDCE (
+ (* abc_arrival=303 *)
+ output reg Q,
+ (* clkbuf_sink *)
+ input C,
+ input CE, D, CLR
+);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -274,7 +286,13 @@ module FDCE (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
endcase endgenerate
endmodule
-module FDPE (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
+module FDPE (
+ (* abc_arrival=303 *)
+ output reg Q,
+ (* clkbuf_sink *)
+ input C,
+ input CE, D, PRE
+);
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -288,38 +306,61 @@ module FDPE (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
endcase endgenerate
endmodule
-module FDRE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
+module FDRE_1 (
+ (* abc_arrival=303 *)
+ output reg Q,
+ (* clkbuf_sink *)
+ input C,
+ input CE, D, R
+);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
endmodule
-module FDSE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
+module FDSE_1 (
+ (* abc_arrival=303 *)
+ output reg Q,
+ (* clkbuf_sink *)
+ input C,
+ input CE, D, S
+);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
endmodule
-module FDCE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
+module FDCE_1 (
+ (* abc_arrival=303 *)
+ output reg Q,
+ (* clkbuf_sink *)
+ input C,
+ input CE, D, CLR
+);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
endmodule
-module FDPE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
+module FDPE_1 (
+ (* abc_arrival=303 *)
+ output reg Q,
+ (* clkbuf_sink *)
+ input C,
+ input CE, D, PRE
+);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule
-(* abc_box_id = 5 *)
module RAM32X1D (
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+ (* abc_arrival=1153 *)
output DPO, SPO,
- (* abc_scc_break *)
input D,
(* clkbuf_sink *)
input WCLK,
- (* abc_scc_break *)
input WE,
input A0, A1, A2, A3, A4,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
@@ -335,14 +376,13 @@ module RAM32X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
-(* abc_box_id = 6 *)
module RAM64X1D (
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+ (* abc_arrival=1153 *)
output DPO, SPO,
- (* abc_scc_break *)
input D,
(* clkbuf_sink *)
input WCLK,
- (* abc_scc_break *)
input WE,
input A0, A1, A2, A3, A4, A5,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
@@ -358,14 +398,13 @@ module RAM64X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
-(* abc_box_id = 7 *)
module RAM128X1D (
- output DPO, SPO,
- (* abc_scc_break *)
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+ (* abc_arrival=1153 *)
+ output DPO, SPO,
input D,
(* clkbuf_sink *)
input WCLK,
- (* abc_scc_break *)
input WE,
input [6:0] A, DPRA
);
@@ -379,6 +418,8 @@ module RAM128X1D (
endmodule
module SRL16E (
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+ (* abc_arrival=1472 *)
output Q,
input A0, A1, A2, A3, CE,
(* clkbuf_sink *)
@@ -423,7 +464,10 @@ module SRLC16E (
endmodule
module SRLC32E (
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+ (* abc_arrival=1472 *)
output Q,
+ (* abc_arrival=1114 *)
output Q31,
input [4:0] A,
input CE,
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 3760a1129..bfc0ac2bf 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -268,9 +268,9 @@ struct SynthXilinxPass : public ScriptPass
{
if (check_label("begin")) {
if (vpr)
- run("read_verilog -lib -icells -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
+ run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
else
- run("read_verilog -lib -icells -D _ABC +/xilinx/cells_sim.v");
+ run("read_verilog -lib +/xilinx/cells_sim.v");
run("read_verilog -lib +/xilinx/cells_xtra.v");
@@ -408,7 +408,7 @@ struct SynthXilinxPass : public ScriptPass
}
if (check_label("map_cells")) {
- std::string techmap_args = "-map +/techmap.v -D _ABC -map +/xilinx/cells_map.v";
+ std::string techmap_args = "-map +/techmap.v -map +/xilinx/cells_map.v";
if (widemux > 0)
techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
run("techmap " + techmap_args);
@@ -428,10 +428,12 @@ struct SynthXilinxPass : public ScriptPass
if (flatten_before_abc)
run("flatten");
if (help_mode)
- run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut', option for '-retime')");
+ run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut'; option for '-retime')");
else if (abc9) {
if (family != "xc7")
log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
+ run("techmap -map +/xilinx/abc_map.v -max_iter 1");
+ run("read_verilog -icells -lib +/xilinx/abc_model.v");
if (nowidelut)
run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
else
@@ -449,14 +451,15 @@ struct SynthXilinxPass : public ScriptPass
// has performed any necessary retiming
if (!nosrl || help_mode)
run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')");
-
std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v";
if (help_mode)
- techmap_args += " [-map +/xilinx/ff_map.v]";
- else if (!abc9)
- techmap_args += " -map +/xilinx/ff_map.v";
+ techmap_args += " [-map +/xilinx/ff_map.v]";
+ else if (abc9)
+ techmap_args += " -map +/xilinx/abc_unmap.v";
+ else
+ techmap_args += " -map +/xilinx/ff_map.v";
run("techmap " + techmap_args);
- if (!abc9)
+ if (!abc9 || help_mode)
run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT", "(without '-abc9' only)");
run("clean");
diff --git a/techlibs/xilinx/xc7_brams_bb.v b/techlibs/xilinx/xc7_brams_bb.v
index a43b4b5a1..5b40a457d 100644
--- a/techlibs/xilinx/xc7_brams_bb.v
+++ b/techlibs/xilinx/xc7_brams_bb.v
@@ -1,3 +1,5 @@
+// Max delays from https://github.com/SymbiFlow/prjxray-db/blob/f8e0364116b2983ac72a3dc8c509ea1cc79e2e3d/artix7/timings/BRAM_L.sdf#L138-L147
+
module RAMB18E1 (
(* clkbuf_sink *)
input CLKARDCLK,
@@ -21,9 +23,13 @@ module RAMB18E1 (
input [1:0] WEA,
input [3:0] WEBWE,
+ (* abc_arrival=2454 *)
output [15:0] DOADO,
+ (* abc_arrival=2454 *)
output [15:0] DOBDO,
+ (* abc_arrival=2454 *)
output [1:0] DOPADOP,
+ (* abc_arrival=2454 *)
output [1:0] DOPBDOP
);
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@@ -147,9 +153,13 @@ module RAMB36E1 (
input [3:0] WEA,
input [7:0] WEBWE,
+ (* abc_arrival=2454 *)
output [31:0] DOADO,
+ (* abc_arrival=2454 *)
output [31:0] DOBDO,
+ (* abc_arrival=2454 *)
output [3:0] DOPADOP,
+ (* abc_arrival=2454 *)
output [3:0] DOPBDOP
);
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-10 16:59:57 +0000