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-rw-r--r--techlibs/xilinx/cells_sim.v4
1 files changed, 0 insertions, 4 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 5143f87da..25df3a865 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -656,7 +656,6 @@ module FDRSE (
Q <= d;
endmodule
-(* lib_whitebox *)
module FDCE (
output reg Q,
(* clkbuf_sink *)
@@ -699,7 +698,6 @@ module FDCE (
endspecify
endmodule
-(* lib_whitebox *)
module FDCE_1 (
output reg Q,
(* clkbuf_sink *)
@@ -724,7 +722,6 @@ module FDCE_1 (
endspecify
endmodule
-(* lib_whitebox *)
module FDPE (
output reg Q,
(* clkbuf_sink *)
@@ -766,7 +763,6 @@ module FDPE (
endspecify
endmodule
-(* lib_whitebox *)
module FDPE_1 (
output reg Q,
(* clkbuf_sink *)