diff options
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 25 |
1 files changed, 3 insertions, 22 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 69b071d34..3d4a65c5d 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -46,7 +46,7 @@ struct SynthXilinxPass : public ScriptPass log(" -top <module>\n"); log(" use the specified module as top module\n"); log("\n"); - log(" -family {xcup|xcu|xc7|xc6v|xc6s}\n"); + log(" -family {xcup|xcu|xc7|xc6v|xc5v|xc6s}\n"); log(" run synthesis for the specified Xilinx architecture\n"); log(" generate the synthesis netlist for the specified family.\n"); log(" default: xc7\n"); @@ -260,7 +260,7 @@ struct SynthXilinxPass : public ScriptPass } extra_args(args, argidx, design); - if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" && family != "xc6s") + if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" && family != "xc5v" && family != "xc6s") log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str()); if (widemux != 0 && widemux < 2) @@ -296,26 +296,7 @@ struct SynthXilinxPass : public ScriptPass else run("read_verilog -lib +/xilinx/cells_sim.v"); - if (help_mode) - run("read_verilog -lib +/xilinx/{family}_cells_xtra.v"); - else if (family == "xc6s") - run("read_verilog -lib +/xilinx/xc6s_cells_xtra.v"); - else if (family == "xc6v") - run("read_verilog -lib +/xilinx/xc6v_cells_xtra.v"); - else if (family == "xc7") - run("read_verilog -lib +/xilinx/xc7_cells_xtra.v"); - else if (family == "xcu" || family == "xcup") - run("read_verilog -lib +/xilinx/xcu_cells_xtra.v"); - - if (help_mode) { - run("read_verilog -lib +/xilinx/{family}_brams_bb.v"); - } else if (family == "xc6s") { - run("read_verilog -lib +/xilinx/xc6s_brams_bb.v"); - } else if (family == "xc6v" || family == "xc7") { - run("read_verilog -lib +/xilinx/xc7_brams_bb.v"); - } else if (family == "xcu" || family == "xcup") { - run("read_verilog -lib +/xilinx/xcu_brams_bb.v"); - } + run("read_verilog -lib +/xilinx/cells_xtra.v"); run(stringf("hierarchy -check %s", top_opt.c_str())); } |