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-rw-r--r--techlibs/xilinx/synth_xilinx.cc5
1 files changed, 1 insertions, 4 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 229ffcb3d..173bdcb91 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -613,10 +613,7 @@ struct SynthXilinxPass : public ScriptPass
if (family != "xc7")
log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
"will use timing for 'xc7' instead.\n", family.c_str());
- std::string techmap_args = "-map +/xilinx/abc9_map.v -max_iter 1";
- if (dff_mode)
- techmap_args += " -D DFF_MODE";
- run("techmap " + techmap_args);
+ run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
run("read_verilog -icells -lib -specify +/abc9_model.v +/xilinx/abc9_model.v");
std::string abc9_opts;
std::string k = "synth_xilinx.abc9.W";