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diff --git a/techlibs/xilinx/lutrams_xc5v.txt b/techlibs/xilinx/lutrams_xc5v.txt
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+# LUT RAMs for Virtex 5, Virtex 6, Spartan 6, Series 7.
+# The corresponding mapping file is lutrams_xc5v_map.v
+
+# Single-port RAMs.
+
+ram distributed $__XILINX_LUTRAM_SP_ {
+	cost 8;
+	widthscale;
+	option "ABITS" 5 {
+		abits 5;
+		widths 8 global;
+	}
+	option "ABITS" 6 {
+		abits 6;
+		widths 4 global;
+	}
+	option "ABITS" 7 {
+		abits 7;
+		widths 2 global;
+	}
+	option "ABITS" 8 {
+		abits 8;
+		widths 1 global;
+	}
+	init no_undef;
+	prune_rom;
+	port arsw "RW" {
+		clock posedge;
+	}
+}
+
+# Dual-port RAMs.
+
+ram distributed $__XILINX_LUTRAM_DP_ {
+	cost 8;
+	widthscale;
+	option "ABITS" 5 {
+		abits 5;
+		widths 4 global;
+	}
+	option "ABITS" 6 {
+		abits 6;
+		widths 2 global;
+	}
+	option "ABITS" 7 {
+		abits 7;
+		widths 1 global;
+	}
+	init no_undef;
+	prune_rom;
+	port arsw "RW" {
+		clock posedge;
+	}
+	port ar "R" {
+	}
+}
+
+# Quad-port RAMs.
+
+ram distributed $__XILINX_LUTRAM_QP_ {
+	cost 7;
+	widthscale;
+	option "ABITS" 5 {
+		abits 5;
+		widths 2 global;
+	}
+	option "ABITS" 6 {
+		abits 6;
+		widths 1 global;
+	}
+	init no_undef;
+	prune_rom;
+	port arsw "RW" {
+		clock posedge;
+	}
+	port ar "R0" "R1" "R2" {
+	}
+}
+
+# Simple dual port RAMs.
+
+ram distributed $__XILINX_LUTRAM_SDP_ {
+	cost 8;
+	widthscale 7;
+	option "ABITS" 5 {
+		abits 5;
+		widths 6 global;
+	}
+	option "ABITS" 6 {
+		abits 6;
+		widths 3 global;
+	}
+	init no_undef;
+	prune_rom;
+	port sw "W" {
+		clock posedge;
+	}
+	port ar "R" {
+	}
+}