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-rw-r--r--techlibs/xilinx/cells_sim.v4
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 910d0e246..bec9ea1a0 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -183,9 +183,9 @@ endmodule
(* abc_box_id = 4, lib_whitebox *)
module CARRY4(
- (* abc_carry_out *) output [3:0] CO,
+ (* abc_carry *) output [3:0] CO,
output [3:0] O,
- (* abc_carry_in *) input CI,
+ (* abc_carry *) input CI,
input CYINIT,
input [3:0] DI, S
);