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-rw-r--r--techlibs/xilinx/cells_sim.v8
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 63223afbf..93d080ffd 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -640,7 +640,7 @@ module FDRSE (
Q <= d;
endmodule
-(* abc9_flop, lib_whitebox *)
+(* lib_whitebox *)
module FDCE (
output reg Q,
(* clkbuf_sink *)
@@ -683,7 +683,7 @@ module FDCE (
endspecify
endmodule
-(* abc9_flop, lib_whitebox *)
+(* lib_whitebox *)
module FDCE_1 (
output reg Q,
(* clkbuf_sink *)
@@ -708,7 +708,7 @@ module FDCE_1 (
endspecify
endmodule
-(* abc9_flop, lib_whitebox *)
+(* lib_whitebox *)
module FDPE (
output reg Q,
(* clkbuf_sink *)
@@ -750,7 +750,7 @@ module FDPE (
endspecify
endmodule
-(* abc9_flop, lib_whitebox *)
+(* lib_whitebox *)
module FDPE_1 (
output reg Q,
(* clkbuf_sink *)