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Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
-rw-r--r-- | techlibs/xilinx/cells_sim.v | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 0b6341938..258999f18 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -384,6 +384,50 @@ module FDPE_1 ( always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule +module LDCE ( + output reg Q, + (* invertible_pin = "IS_CLR_INVERTED" *) + input CLR, + input D, + (* invertible_pin = "IS_G_INVERTED" *) + input G, + input GE +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_CLR_INVERTED = 1'b0; + parameter [0:0] IS_G_INVERTED = 1'b0; + parameter MSGON = "TRUE"; + parameter XON = "TRUE"; + initial Q = INIT; + wire clr = CLR ^ IS_CLR_INVERTED; + wire g = G ^ IS_G_INVERTED; + always @* + if (clr) Q = 1'b0; + else if (GE && g) Q = D; +endmodule + +module LDPE ( + output reg Q, + input D, + (* invertible_pin = "IS_G_INVERTED" *) + input G, + input GE, + (* invertible_pin = "IS_PRE_INVERTED" *) + input PRE +); + parameter [0:0] INIT = 1'b1; + parameter [0:0] IS_G_INVERTED = 1'b0; + parameter [0:0] IS_PRE_INVERTED = 1'b0; + parameter MSGON = "TRUE"; + parameter XON = "TRUE"; + initial Q = INIT; + wire g = G ^ IS_G_INVERTED; + wire pre = PRE ^ IS_PRE_INVERTED; + always @* + if (pre) Q = 1'b1; + else if (GE && g) Q = D; +endmodule + module RAM32X1D ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 (* abc_arrival=1153 *) |