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-rw-r--r--techlibs/xilinx/abc_xc7.box10
1 files changed, 5 insertions, 5 deletions
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 67d1ffb1e..b1c24ed24 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -16,7 +16,7 @@ MUXF8 2 1 3 1
# Inputs: I0 I1 I2 I3 S0 S1
# Outputs: O
-MUXF78 10 1 6 1
+MUXF78 3 1 6 1
190 193 217 223 296 273
# CARRY4 + CARRY4_[ABCD]X
@@ -25,7 +25,7 @@ MUXF78 10 1 6 1
# (NB: carry chain input/output must be last
# input/output and have been moved there
# overriding the alphabetical ordering)
-CARRY4 3 1 10 8
+CARRY4 4 1 10 8
482 - - - - 223 - - - 222
598 407 - - - 400 205 - - 334
584 556 537 - - 523 558 226 - 239
@@ -38,20 +38,20 @@ CARRY4 3 1 10 8
# SLICEM/A6LUT
# Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE
# Outputs: DPO SPO
-RAM32X1D 4 0 13 2
+RAM32X1D 5 0 13 2
- - - - - - 631 472 407 238 127 - -
631 472 407 238 127 - - - - - - - -
# SLICEM/A6LUT
# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
# Outputs: DPO SPO
-RAM64X1D 5 0 15 2
+RAM64X1D 6 0 15 2
- - - - - - - 642 631 472 407 238 127 - -
642 631 472 407 238 127 - - - - - - - - -
# SLICEM/A6LUT + F7[AB]MUX
# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
# Outputs: DPO SPO
-RAM128X1D 6 0 17 2
+RAM128X1D 7 0 17 2
- - - - - - - - 1009 998 839 774 605 494 450 - -
1047 1036 877 812 643 532 478 - - - - - - - - - -