aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/xilinx/abc9_model.v
diff options
context:
space:
mode:
Diffstat (limited to 'techlibs/xilinx/abc9_model.v')
-rw-r--r--techlibs/xilinx/abc9_model.v170
1 files changed, 150 insertions, 20 deletions
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v
index 15d12c89f..2d109ef8a 100644
--- a/techlibs/xilinx/abc9_model.v
+++ b/techlibs/xilinx/abc9_model.v
@@ -24,25 +24,40 @@
// Necessary to make these an atomic unit so that
// ABC cannot optimise just one of the MUXF7 away
// and expect to save on its delay
-(* abc9_box_id = 3, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
assign O = S1 ? (S0 ? I3 : I2)
: (S0 ? I1 : I0);
-endmodule
-
-module \$__ABC9_FF_ (input D, output Q);
+ specify
+ (I0 => O) = 294;
+ (I1 => O) = 297;
+ (I2 => O) = 311;
+ (I3 => O) = 317;
+ (S0 => O) = 390;
+ (S1 => O) = 273;
+ endspecify
endmodule
// Box to emulate async behaviour of FDC*
-(* abc9_box_id = 1000, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
module \$__ABC9_ASYNC0 (input A, S, output Y);
assign Y = S ? 1'b0 : A;
+ specify
+ (A => Y) = 0;
+ // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
+ (S => Y) = 764;
+ endspecify
endmodule
// Box to emulate async behaviour of FDP*
-(* abc9_box_id = 1001, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
module \$__ABC9_ASYNC1 (input A, S, output Y);
assign Y = S ? 1'b1 : A;
+ specify
+ (A => Y) = 0;
+ // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
+ (S => Y) = 764;
+ endspecify
endmodule
// Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32}
@@ -51,18 +66,37 @@ endmodule
// is only committed on the next clock edge).
// To model the combinatorial path, such cells have to be split
// into comb and seq parts, with this box modelling only the former.
-(* abc9_box_id=2000 *)
-module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
+(* abc9_box *)
+module \$__ABC9_RAM6 (input A, input [5:0] S, output Y);
+ specify
+ (A => Y) = 0;
+ (S[0] => Y) = 642;
+ (S[1] => Y) = 631;
+ (S[2] => Y) = 472;
+ (S[3] => Y) = 407;
+ (S[4] => Y) = 238;
+ (S[5] => Y) = 127;
+ endspecify
endmodule
// Box to emulate comb/seq behaviour of RAM128
-(* abc9_box_id=2001 *)
-module \$__ABC9_LUT7 (input A, input [6:0] S, output Y);
+(* abc9_box *)
+module \$__ABC9_RAM7 (input A, input [6:0] S, output Y);
+ specify
+ (A => Y) = 0;
+ // https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L867
+ (S[0] => Y) = 642 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
+ (S[1] => Y) = 631 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
+ (S[2] => Y) = 472 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
+ (S[3] => Y) = 407 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
+ (S[4] => Y) = 238 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
+ (S[5] => Y) = 127 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
+ (S[6] => Y) = 0 + 296 /* to select F7BMUX */ + 174 /* CMUX */;
+ endspecify
endmodule
-// Boxes used to represent the comb behaviour of various modes
-// of DSP48E1
-`define ABC9_DSP48E1(__NAME__) """
-module __NAME__ (
+// Boxes used to represent the comb behaviour of DSP48E1
+(* abc9_box *)
+module $__ABC9_DSP48E1 (
input [29:0] $A,
input [17:0] $B,
input [47:0] $C,
@@ -71,10 +105,106 @@ module __NAME__ (
input [47:0] $PCIN,
input [47:0] $PCOUT,
output [47:0] P,
- output [47:0] PCOUT);
+ output [47:0] PCOUT
+);
+ parameter integer ADREG = 1;
+ parameter integer AREG = 1;
+ parameter integer BREG = 1;
+ parameter integer CREG = 1;
+ parameter integer DREG = 1;
+ parameter integer MREG = 1;
+ parameter integer PREG = 1;
+ parameter USE_DPORT = "FALSE";
+ parameter USE_MULT = "MULTIPLY";
+
+ function integer \A.P.comb ;
+ begin
+ if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.P.comb = 2823;
+ else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.P.comb = 3806;
+ else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.P.comb = 1523;
+ end
+ endfunction
+ function integer \A.PCOUT.comb ;
+ begin
+ if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.PCOUT.comb = 2970;
+ else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.PCOUT.comb = 3954;
+ else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.PCOUT.comb = 1671;
+ end
+ endfunction
+ function integer \B.P.comb ;
+ begin
+ if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.P.comb = 2690;
+ else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.P.comb = 2690;
+ else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.P.comb = 1509;
+ end
+ endfunction
+ function integer \B.PCOUT.comb ;
+ begin
+ if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.PCOUT.comb = 2838;
+ else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.PCOUT.comb = 2838;
+ else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.PCOUT.comb = 1658;
+ end
+ endfunction
+ function integer \C.P.comb ;
+ begin
+ if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.P.comb = 1325;
+ else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.P.comb = 1325;
+ else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.P.comb = 1325;
+ end
+ endfunction
+ function integer \C.PCOUT.comb ;
+ begin
+ if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474;
+ else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.PCOUT.comb = 1474;
+ else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474;
+ end
+ endfunction
+ function integer \D.P.comb ;
+ begin
+ if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.P.comb = 3717;
+ end
+ endfunction
+ function integer \D.PCOUT.comb ;
+ begin
+ if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.PCOUT.comb = 3700;
+ end
+ endfunction
+
+ specify
+ ($P *> P) = 0;
+ ($PCOUT *> PCOUT) = 0;
+ endspecify
+
+ // Identical comb delays to DSP48E1 in cells_sim.v
+ generate
+ if (PREG == 0 && MREG == 0 && AREG == 0 && ADREG == 0)
+ specify
+ ($A *> P) = \A.P.comb ();
+ ($A *> PCOUT) = \A.PCOUT.comb ();
+ endspecify
+
+ if (PREG == 0 && MREG == 0 && BREG == 0)
+ specify
+ ($B *> P) = \B.P.comb ();
+ ($B *> PCOUT) = \B.PCOUT.comb ();
+ endspecify
+
+ if (PREG == 0 && CREG == 0)
+ specify
+ ($C *> P) = \C.P.comb ();
+ ($C *> PCOUT) = \C.PCOUT.comb ();
+ endspecify
+
+ if (PREG == 0 && MREG == 0 && ADREG == 0 && DREG == 0)
+ specify
+ ($D *> P) = \D.P.comb ();
+ ($D *> PCOUT) = \D.PCOUT.comb ();
+ endspecify
+
+ if (PREG == 0)
+ specify
+ ($PCIN *> P) = 1107;
+ ($PCIN *> PCOUT) = 1255;
+ endspecify
+ endgenerate
endmodule
-"""
-(* abc9_box_id=3000 *) `ABC9_DSP48E1($__ABC9_DSP48E1_MULT)
-(* abc9_box_id=3001 *) `ABC9_DSP48E1($__ABC9_DSP48E1_MULT_DPORT)
-(* abc9_box_id=3002 *) `ABC9_DSP48E1($__ABC9_DSP48E1)
-`undef ABC9_DSP48E1
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-27 03:10:58 +0000