diff options
Diffstat (limited to 'techlibs/sf2')
| -rw-r--r-- | techlibs/sf2/arith_map.v | 2 | ||||
| -rw-r--r-- | techlibs/sf2/cells_sim.v | 6 | ||||
| -rw-r--r-- | techlibs/sf2/synth_sf2.cc | 3 |
3 files changed, 6 insertions, 5 deletions
diff --git a/techlibs/sf2/arith_map.v b/techlibs/sf2/arith_map.v index 462d3ce50..f16b1abb8 100644 --- a/techlibs/sf2/arith_map.v +++ b/techlibs/sf2/arith_map.v @@ -1,7 +1,7 @@ /* * yosys -- Yosys Open SYnthesis Suite * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/techlibs/sf2/cells_sim.v b/techlibs/sf2/cells_sim.v index eff57a655..4b57bad7b 100644 --- a/techlibs/sf2/cells_sim.v +++ b/techlibs/sf2/cells_sim.v @@ -1,20 +1,20 @@ // https://coredocs.s3.amazonaws.com/Libero/12_0_0/Tool/sf2_mlg.pdf -module ADD2 ( +module AND2 ( input A, B, output Y ); assign Y = A & B; endmodule -module ADD3 ( +module AND3 ( input A, B, C, output Y ); assign Y = A & B & C; endmodule -module ADD4 ( +module AND4 ( input A, B, C, D, output Y ); diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc index a0061ebd0..8d78a6097 100644 --- a/techlibs/sf2/synth_sf2.cc +++ b/techlibs/sf2/synth_sf2.cc @@ -1,7 +1,7 @@ /* * yosys -- Yosys Open SYnthesis Suite * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -228,6 +228,7 @@ struct SynthSf2Pass : public ScriptPass run("hierarchy -check"); run("stat"); run("check -noinit"); + run("blackbox =A:whitebox"); } if (check_label("edif")) |