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-rw-r--r--techlibs/intel_alm/common/misc_sim.v9
1 files changed, 9 insertions, 0 deletions
diff --git a/techlibs/intel_alm/common/misc_sim.v b/techlibs/intel_alm/common/misc_sim.v
index e9494a8ee..b1f970a21 100644
--- a/techlibs/intel_alm/common/misc_sim.v
+++ b/techlibs/intel_alm/common/misc_sim.v
@@ -10,3 +10,12 @@ module MISTRAL_IO((* iopad_external_pin *) inout PAD, input I, input OE, output
assign PAD = OE ? I : 1'bz;
assign O = PAD;
endmodule
+
+// Eventually, we should support clock enables and model them here too.
+// For now, CLKENA is used as a basic entry point to global routing.
+module MISTRAL_CLKBUF (
+ input A,
+ (* clkbuf_driver *) output Q
+);
+ assign Q = A;
+endmodule \ No newline at end of file