diff options
Diffstat (limited to 'techlibs/intel_alm/common/mem_sim.v')
| -rw-r--r-- | techlibs/intel_alm/common/mem_sim.v | 50 |
1 files changed, 47 insertions, 3 deletions
diff --git a/techlibs/intel_alm/common/mem_sim.v b/techlibs/intel_alm/common/mem_sim.v index dbdf69839..370e17f27 100644 --- a/techlibs/intel_alm/common/mem_sim.v +++ b/techlibs/intel_alm/common/mem_sim.v @@ -56,6 +56,33 @@ module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, reg [31:0] mem = 32'b0; +`ifdef cyclonev +specify + $setup(A1ADDR, posedge CLK1, 86); + $setup(A1DATA, posedge CLK1, 86); + $setup(A1EN, posedge CLK1, 86); + + (B1ADDR[0] => B1DATA) = 487; + (B1ADDR[1] => B1DATA) = 475; + (B1ADDR[2] => B1DATA) = 382; + (B1ADDR[3] => B1DATA) = 284; + (B1ADDR[4] => B1DATA) = 96; +endspecify +`endif +`ifdef arriav +specify + $setup(A1ADDR, posedge CLK1, 62); + $setup(A1DATA, posedge CLK1, 62); + $setup(A1EN, posedge CLK1, 62); + + (B1ADDR[0] => B1DATA) = 370; + (B1ADDR[1] => B1DATA) = 292; + (B1ADDR[2] => B1DATA) = 218; + (B1ADDR[3] => B1DATA) = 74; + (B1ADDR[4] => B1DATA) = 177; +endspecify +`endif +`ifdef cyclone10gx // TODO: Cyclone 10 GX timings; the below timings are for Cyclone V specify $setup(A1ADDR, posedge CLK1, 86); @@ -68,6 +95,7 @@ specify (B1ADDR[3] => B1DATA) = 284; (B1ADDR[4] => B1DATA) = 96; endspecify +`endif always @(posedge CLK1) if (A1EN) mem[A1ADDR] <= A1DATA; @@ -93,12 +121,28 @@ output reg [CFG_DBITS-1:0] B1DATA; reg [2**CFG_ABITS * CFG_DBITS - 1 : 0] mem = 0; +`ifdef cyclonev +specify + $setup(A1ADDR, posedge CLK1, 125); + $setup(A1DATA, posedge CLK1, 97); + $setup(A1EN, posedge CLK1, 140); + $setup(B1ADDR, posedge CLK1, 125); + $setup(B1EN, posedge CLK1, 161); + + if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 1004; +endspecify +`endif +`ifdef arriav specify - $setup(A1ADDR, posedge CLK1, 0); - $setup(A1DATA, posedge CLK1, 0); + $setup(A1ADDR, posedge CLK1, 97); + $setup(A1DATA, posedge CLK1, 74); + $setup(A1EN, posedge CLK1, 109); + $setup(B1ADDR, posedge CLK1, 97); + $setup(B1EN, posedge CLK1, 126); - if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 0; + if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 787; endspecify +`endif always @(posedge CLK1) begin if (A1EN) |