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-rw-r--r--techlibs/intel/cyclonev/cells_sim.v2
-rw-r--r--techlibs/intel/synth_intel.cc4
2 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/intel/cyclonev/cells_sim.v b/techlibs/intel/cyclonev/cells_sim.v
index 5ecdabcfc..fa27c2c8e 100644
--- a/techlibs/intel/cyclonev/cells_sim.v
+++ b/techlibs/intel/cyclonev/cells_sim.v
@@ -54,7 +54,7 @@ module cyclonev_lcell_comb
// Internal variables
// Sub mask for fragmented LUTs
wire [15:0] mask_a, mask_b, mask_c, mask_d;
- // Independant output for fragmented LUTs
+ // Independent output for fragmented LUTs
wire output_0, output_1, output_2, output_3;
// Extended mode uses mux to define the output
wire mux_0, mux_1;
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index d74f295ec..0f1d7a7b5 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -131,8 +131,8 @@ struct SynthIntelPass : public ScriptPass {
nobram = true;
continue;
}
- if (args[argidx] == "-flatten") {
- flatten = true;
+ if (args[argidx] == "-noflatten") {
+ flatten = false;
continue;
}
if (args[argidx] == "-retime") {