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Diffstat (limited to 'techlibs/intel/cyclonev/cells_map.v')
| -rw-r--r-- | techlibs/intel/cyclonev/cells_map.v | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/intel/cyclonev/cells_map.v b/techlibs/intel/cyclonev/cells_map.v index f8d142bc9..eb4cd54d1 100644 --- a/techlibs/intel/cyclonev/cells_map.v +++ b/techlibs/intel/cyclonev/cells_map.v @@ -71,6 +71,7 @@ endmodule module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; + (* force_downto *) input [WIDTH-1:0] A; output Y; wire VCC; |