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-rw-r--r--techlibs/ice40/cells_sim.v102
1 files changed, 61 insertions, 41 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 4dc011be4..13d04b2ed 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -246,12 +246,12 @@ endmodule
// SiliconBlue RAM Cells
module SB_RAM40_4K (
- output reg [15:0] RDATA,
- input RCLK, RCLKE, RE,
- input [10:0] RADDR,
- input WCLK, WCLKE, WE,
- input [10:0] WADDR,
- input [15:0] MASK, WDATA
+ output [15:0] RDATA,
+ input RCLK, RCLKE, RE,
+ input [10:0] RADDR,
+ input WCLK, WCLKE, WE,
+ input [10:0] WADDR,
+ input [15:0] MASK, WDATA
);
// MODE 0: 256 x 16
// MODE 1: 512 x 8
@@ -278,6 +278,26 @@ module SB_RAM40_4K (
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
`ifndef BLACKBOX
+ reg [15:0] RDATA_I;
+ wire [15:0] WDATA_I;
+
+ generate
+ case (WRITE_MODE)
+ 0: assign WDATA_I = WDATA;
+ 1: assign WDATA_I = {WDATA[14], WDATA[12], WDATA[10], WDATA[ 8],
+ WDATA[ 6], WDATA[ 4], WDATA[ 2], WDATA[ 0]};
+ 2: assign WDATA_I = {WDATA[13], WDATA[9], WDATA[5], WDATA[1]};
+ 3: assign WDATA_I = {WDATA[11], WDATA[3]};
+ endcase
+ case (READ_MODE)
+ 0: assign RDATA = RDATA_I;
+ 1: assign RDATA = {1'b0, RDATA_I[7], 1'b0, RDATA_I[6], 1'b0, RDATA_I[5], 1'b0, RDATA_I[4],
+ 1'b0, RDATA_I[3], 1'b0, RDATA_I[2], 1'b0, RDATA_I[1], 1'b0, RDATA_I[0]};
+ 2: assign RDATA = {2'b00, RDATA_I[3], 3'b000, RDATA_I[2], 3'b000, RDATA_I[1], 3'b000, RDATA_I[0], 1'b0};
+ 3: assign RDATA = {4'b0000, RDATA_I[1], 7'b0000000, RDATA_I[0], 3'b000};
+ endcase
+ endgenerate
+
integer i;
reg [15:0] memory [0:255];
@@ -305,43 +325,43 @@ module SB_RAM40_4K (
always @(posedge WCLK) begin
if (WE && WCLKE) begin
if (WRITE_MODE == 0) begin
- if (MASK[ 0]) memory[WADDR[7:0]][ 0] <= WDATA[ 0];
- if (MASK[ 1]) memory[WADDR[7:0]][ 1] <= WDATA[ 1];
- if (MASK[ 2]) memory[WADDR[7:0]][ 2] <= WDATA[ 2];
- if (MASK[ 3]) memory[WADDR[7:0]][ 3] <= WDATA[ 3];
- if (MASK[ 4]) memory[WADDR[7:0]][ 4] <= WDATA[ 4];
- if (MASK[ 5]) memory[WADDR[7:0]][ 5] <= WDATA[ 5];
- if (MASK[ 6]) memory[WADDR[7:0]][ 6] <= WDATA[ 6];
- if (MASK[ 7]) memory[WADDR[7:0]][ 7] <= WDATA[ 7];
- if (MASK[ 8]) memory[WADDR[7:0]][ 8] <= WDATA[ 8];
- if (MASK[ 9]) memory[WADDR[7:0]][ 9] <= WDATA[ 9];
- if (MASK[10]) memory[WADDR[7:0]][10] <= WDATA[10];
- if (MASK[11]) memory[WADDR[7:0]][11] <= WDATA[11];
- if (MASK[12]) memory[WADDR[7:0]][12] <= WDATA[12];
- if (MASK[13]) memory[WADDR[7:0]][13] <= WDATA[13];
- if (MASK[14]) memory[WADDR[7:0]][14] <= WDATA[14];
- if (MASK[15]) memory[WADDR[7:0]][15] <= WDATA[15];
- if (MASK[16]) memory[WADDR[7:0]][16] <= WDATA[16];
+ if (!MASK[ 0]) memory[WADDR[7:0]][ 0] <= WDATA_I[ 0];
+ if (!MASK[ 1]) memory[WADDR[7:0]][ 1] <= WDATA_I[ 1];
+ if (!MASK[ 2]) memory[WADDR[7:0]][ 2] <= WDATA_I[ 2];
+ if (!MASK[ 3]) memory[WADDR[7:0]][ 3] <= WDATA_I[ 3];
+ if (!MASK[ 4]) memory[WADDR[7:0]][ 4] <= WDATA_I[ 4];
+ if (!MASK[ 5]) memory[WADDR[7:0]][ 5] <= WDATA_I[ 5];
+ if (!MASK[ 6]) memory[WADDR[7:0]][ 6] <= WDATA_I[ 6];
+ if (!MASK[ 7]) memory[WADDR[7:0]][ 7] <= WDATA_I[ 7];
+ if (!MASK[ 8]) memory[WADDR[7:0]][ 8] <= WDATA_I[ 8];
+ if (!MASK[ 9]) memory[WADDR[7:0]][ 9] <= WDATA_I[ 9];
+ if (!MASK[10]) memory[WADDR[7:0]][10] <= WDATA_I[10];
+ if (!MASK[11]) memory[WADDR[7:0]][11] <= WDATA_I[11];
+ if (!MASK[12]) memory[WADDR[7:0]][12] <= WDATA_I[12];
+ if (!MASK[13]) memory[WADDR[7:0]][13] <= WDATA_I[13];
+ if (!MASK[14]) memory[WADDR[7:0]][14] <= WDATA_I[14];
+ if (!MASK[15]) memory[WADDR[7:0]][15] <= WDATA_I[15];
+ if (!MASK[16]) memory[WADDR[7:0]][16] <= WDATA_I[16];
end
if (WRITE_MODE == 1) begin
- if (WADDR[0] == 0) memory[WADDR[8:1]][0*8 +: 8] <= WDATA[7:0];
- if (WADDR[0] == 1) memory[WADDR[8:1]][1*8 +: 8] <= WDATA[7:0];
+ if (WADDR[0] == 0) memory[WADDR[8:1]][0*8 +: 8] <= WDATA_I[7:0];
+ if (WADDR[0] == 1) memory[WADDR[8:1]][1*8 +: 8] <= WDATA_I[7:0];
end
if (WRITE_MODE == 2) begin
- if (WADDR[1:0] == 0) memory[WADDR[9:2]][0*4 +: 4] <= WDATA[3:0];
- if (WADDR[1:0] == 1) memory[WADDR[9:2]][1*4 +: 4] <= WDATA[3:0];
- if (WADDR[1:0] == 2) memory[WADDR[9:2]][2*4 +: 4] <= WDATA[3:0];
- if (WADDR[1:0] == 3) memory[WADDR[9:2]][3*4 +: 4] <= WDATA[3:0];
+ if (WADDR[1:0] == 0) memory[WADDR[9:2]][0*4 +: 4] <= WDATA_I[3:0];
+ if (WADDR[1:0] == 1) memory[WADDR[9:2]][1*4 +: 4] <= WDATA_I[3:0];
+ if (WADDR[1:0] == 2) memory[WADDR[9:2]][2*4 +: 4] <= WDATA_I[3:0];
+ if (WADDR[1:0] == 3) memory[WADDR[9:2]][3*4 +: 4] <= WDATA_I[3:0];
end
if (WRITE_MODE == 3) begin
- if (WADDR[2:0] == 0) memory[WADDR[10:3]][0*2 +: 2] <= WDATA[1:0];
- if (WADDR[2:0] == 1) memory[WADDR[10:3]][1*2 +: 2] <= WDATA[1:0];
- if (WADDR[2:0] == 2) memory[WADDR[10:3]][2*2 +: 2] <= WDATA[1:0];
- if (WADDR[2:0] == 3) memory[WADDR[10:3]][3*2 +: 2] <= WDATA[1:0];
- if (WADDR[2:0] == 4) memory[WADDR[10:3]][4*2 +: 2] <= WDATA[1:0];
- if (WADDR[2:0] == 5) memory[WADDR[10:3]][5*2 +: 2] <= WDATA[1:0];
- if (WADDR[2:0] == 6) memory[WADDR[10:3]][6*2 +: 2] <= WDATA[1:0];
- if (WADDR[2:0] == 7) memory[WADDR[10:3]][7*2 +: 2] <= WDATA[1:0];
+ if (WADDR[2:0] == 0) memory[WADDR[10:3]][0*2 +: 2] <= WDATA_I[1:0];
+ if (WADDR[2:0] == 1) memory[WADDR[10:3]][1*2 +: 2] <= WDATA_I[1:0];
+ if (WADDR[2:0] == 2) memory[WADDR[10:3]][2*2 +: 2] <= WDATA_I[1:0];
+ if (WADDR[2:0] == 3) memory[WADDR[10:3]][3*2 +: 2] <= WDATA_I[1:0];
+ if (WADDR[2:0] == 4) memory[WADDR[10:3]][4*2 +: 2] <= WDATA_I[1:0];
+ if (WADDR[2:0] == 5) memory[WADDR[10:3]][5*2 +: 2] <= WDATA_I[1:0];
+ if (WADDR[2:0] == 6) memory[WADDR[10:3]][6*2 +: 2] <= WDATA_I[1:0];
+ if (WADDR[2:0] == 7) memory[WADDR[10:3]][7*2 +: 2] <= WDATA_I[1:0];
end
end
end
@@ -349,16 +369,16 @@ module SB_RAM40_4K (
always @(posedge RCLK) begin
if (RE && RCLKE) begin
if (READ_MODE == 0) begin
- RDATA <= memory[RADDR[7:0]];
+ RDATA_I <= memory[RADDR[7:0]];
end
if (READ_MODE == 1) begin
- RDATA <= memory[RADDR[8:1]][RADDR[0]*8 +: 8];
+ RDATA_I <= memory[RADDR[8:1]][RADDR[0]*8 +: 8];
end
if (READ_MODE == 2) begin
- RDATA <= memory[RADDR[9:2]][RADDR[1:0]*4 +: 4];
+ RDATA_I <= memory[RADDR[9:2]][RADDR[1:0]*4 +: 4];
end
if (READ_MODE == 3) begin
- RDATA <= memory[RADDR[10:3]][RADDR[2:0]*2 +: 2];
+ RDATA_I <= memory[RADDR[10:3]][RADDR[2:0]*2 +: 2];
end
end
end
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-01 07:51:15 +0000