diff options
Diffstat (limited to 'techlibs/gowin/synth_gowin.cc')
-rw-r--r-- | techlibs/gowin/synth_gowin.cc | 82 |
1 files changed, 41 insertions, 41 deletions
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index a44bbe2f6..a95d81bfd 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -32,46 +32,46 @@ struct SynthGowinPass : public ScriptPass void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" synth_gowin [options]\n"); - log("\n"); - log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n"); - log("\n"); - log(" -top <module>\n"); - log(" use the specified module as top module (default='top')\n"); - log("\n"); - log(" -vout <file>\n"); - log(" write the design to the specified Verilog netlist file. writing of an\n"); - log(" output file is omitted if this parameter is not specified.\n"); - log("\n"); - log(" -run <from_label>:<to_label>\n"); - log(" only run the commands between the labels (see below). an empty\n"); - log(" from label is synonymous to 'begin', and empty to label is\n"); - log(" synonymous to the end of the command list.\n"); - log("\n"); - log(" -nodffe\n"); - log(" do not use flipflops with CE in output netlist\n"); - log("\n"); - log(" -nobram\n"); - log(" do not use BRAM cells in output netlist\n"); - log("\n"); - log(" -nodram\n"); - log(" do not use distributed RAM cells in output netlist\n"); - log("\n"); - log(" -noflatten\n"); - log(" do not flatten design before synthesis\n"); - log("\n"); - log(" -retime\n"); - log(" run 'abc' with -dff option\n"); - log("\n"); - log(" -nowidelut\n"); - log(" do not use muxes to implement LUTs larger than LUT4s\n"); - log("\n"); - log(" -abc9\n"); - log(" use new ABC9 flow (EXPERIMENTAL)\n"); - log("\n"); - log("\n"); - log("The following commands are executed by this synthesis command:\n"); + log("\n"); + log(" synth_gowin [options]\n"); + log("\n"); + log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n"); + log("\n"); + log(" -top <module>\n"); + log(" use the specified module as top module (default='top')\n"); + log("\n"); + log(" -vout <file>\n"); + log(" write the design to the specified Verilog netlist file. writing of an\n"); + log(" output file is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -run <from_label>:<to_label>\n"); + log(" only run the commands between the labels (see below). an empty\n"); + log(" from label is synonymous to 'begin', and empty to label is\n"); + log(" synonymous to the end of the command list.\n"); + log("\n"); + log(" -nodffe\n"); + log(" do not use flipflops with CE in output netlist\n"); + log("\n"); + log(" -nobram\n"); + log(" do not use BRAM cells in output netlist\n"); + log("\n"); + log(" -nodram\n"); + log(" do not use distributed RAM cells in output netlist\n"); + log("\n"); + log(" -noflatten\n"); + log(" do not flatten design before synthesis\n"); + log("\n"); + log(" -retime\n"); + log(" run 'abc' with -dff option\n"); + log("\n"); + log(" -nowidelut\n"); + log(" do not use muxes to implement LUTs larger than LUT4s\n"); + log("\n"); + log(" -abc9\n"); + log(" use new ABC9 flow (EXPERIMENTAL)\n"); + log("\n"); + log("\n"); + log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } @@ -237,7 +237,7 @@ struct SynthGowinPass : public ScriptPass run("setundef -undriven -params -zero"); run("hilomap -singleton -hicell VCC V -locell GND G"); run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)"); - run("dffinit -ff DFF Q INIT"); + run("dffinit -ff DFF Q INIT"); run("clean"); } |