1 files changed, 68 insertions, 1 deletions
diff --git a/techlibs/gatemate/cells_bb.v b/techlibs/gatemate/cells_bb.v
index 3a1fcd550..f6fe6a3e1 100644
--- a/techlibs/gatemate/cells_bb.v
+++ b/techlibs/gatemate/cells_bb.v
@@ -45,7 +45,7 @@ module CC_PLL_ADV #(
 );
 endmodule
 
-(* blackbox *)
+(* blackbox *) (* keep *)
 module CC_SERDES #(
 	parameter SERDES_CFG = ""
 )(
@@ -122,3 +122,70 @@ module CC_CFG_CTRL(
 	input VALID
 );
 endmodule
+
+(* blackbox *)
+module CC_FIFO_40K (
+	output A_ECC_1B_ERR,
+	output B_ECC_1B_ERR,
+	output A_ECC_2B_ERR,
+	output B_ECC_2B_ERR,
+	// FIFO pop port
+	output [39:0] A_DO,
+	output [39:0] B_DO,
+	(* clkbuf_sink *)
+	input  A_CLK,
+	input  A_EN,
+	// FIFO push port
+	input  [39:0] A_DI,
+	input  [39:0] B_DI,
+	input  [39:0] A_BM,
+	input  [39:0] B_BM,
+	(* clkbuf_sink *)
+	input  B_CLK,
+	input  B_EN,
+	input  B_WE,
+	// FIFO control
+	input  F_RST_N,
+	input  [12:0] F_ALMOST_FULL_OFFSET,
+	input  [12:0] F_ALMOST_EMPTY_OFFSET,
+	// FIFO status signals
+	output F_FULL,
+	output F_EMPTY,
+	output F_ALMOST_FULL,
+	output F_ALMOST_EMPTY,
+	output F_RD_ERROR,
+	output F_WR_ERROR,
+	output [15:0] F_RD_PTR,
+	output [15:0] F_WR_PTR
+);
+	// Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED
+	parameter LOC = "UNPLACED";
+
+	// Offset configuration
+	parameter [12:0] ALMOST_FULL_OFFSET = 12'b0;
+	parameter [12:0] ALMOST_EMPTY_OFFSET = 12'b0;
+
+	// Port Widths
+	parameter A_WIDTH = 0;
+	parameter B_WIDTH = 0;
+
+	// RAM and Write Modes
+	parameter RAM_MODE = "SDP"; // "TPD" or "SDP"
+	parameter FIFO_MODE = "SYNC"; // "ASYNC" or "SYNC"
+
+	// Inverting Control Pins
+	parameter A_CLK_INV = 1'b0;
+	parameter B_CLK_INV = 1'b0;
+	parameter A_EN_INV = 1'b0;
+	parameter B_EN_INV = 1'b0;
+	parameter A_WE_INV = 1'b0;
+	parameter B_WE_INV = 1'b0;
+
+	// Output Register
+	parameter A_DO_REG = 1'b0;
+	parameter B_DO_REG = 1'b0;
+
+	// Error Checking and Correction
+	parameter A_ECC_EN  = 1'b0;
+	parameter B_ECC_EN  = 1'b0;
+endmodule