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-rw-r--r--techlibs/ecp5/cells_sim.v4
-rw-r--r--techlibs/ecp5/synth_ecp5.cc4
2 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 507ab1beb..f27540bd7 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -57,7 +57,7 @@ module TRELLIS_RAM16X2 (
input RAD0, RAD1, RAD2, RAD3,
output DO0, DO1
);
- parameter WCKMUX = "WCK";
+ parameter WCKMUX = "WCK";
parameter WREMUX = "WRE";
parameter INITVAL_0 = 16'h0000;
parameter INITVAL_1 = 16'h0000;
@@ -104,7 +104,7 @@ module TRELLIS_DPR16X4 (
input [3:0] RAD,
output [3:0] DO
);
- parameter WCKMUX = "WCK";
+ parameter WCKMUX = "WCK";
parameter WREMUX = "WRE";
parameter [63:0] INITVAL = 64'h0000000000000000;
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 2e9176a84..bda03d251 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -268,9 +268,9 @@ struct SynthEcp5Pass : public ScriptPass
}
run("techmap -map +/ecp5/latches_map.v");
if (nomux)
- run("abc -lut 4");
+ run("abc -lut 4 -dress");
else
- run("abc -lut 4:7");
+ run("abc -lut 4:7 -dress");
run("clean");
}