diff options
Diffstat (limited to 'techlibs/common')
-rw-r--r-- | techlibs/common/simlib.v | 16 | ||||
-rw-r--r-- | techlibs/common/techmap.v | 12 |
2 files changed, 28 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 465efc0a7..c170945ea 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -443,6 +443,22 @@ endmodule // -------------------------------------------------------- +module \$fa (A, B, C, X, Y); + +parameter WIDTH = 1; + +input [WIDTH-1:0] A, B, C; +output [WIDTH-1:0] X, Y; + +wire [WIDTH-1:0] t1, t2, t3; + +assign t1 = A ^ B, t2 = A & B, t3 = C & t1; +assign Y = t1 ^ C, X = t2 | t3; + +endmodule + +// -------------------------------------------------------- + module \$alu (A, B, CI, BI, X, Y, CO); parameter A_SIGNED = 0; diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index dc52ca5fa..050746376 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -246,6 +246,18 @@ endmodule // ALU Infrastructure // -------------------------------------------------------- +module \$fa (A, B, C, X, Y); + parameter WIDTH = 1; + + input [WIDTH-1:0] A, B, C; + output [WIDTH-1:0] X, Y; + + wire [WIDTH-1:0] t1, t2, t3; + + assign t1 = A ^ B, t2 = A & B, t3 = C & t1; + assign Y = t1 ^ C, X = t2 | t3; +endmodule + module \$__alu_ripple (A, B, CI, X, Y, CO); parameter WIDTH = 1; |