diff options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 5 | ||||
| -rw-r--r-- | passes/techmap/techmap.cc | 9 |
2 files changed, 11 insertions, 3 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 4786aacaf..3534cbcdb 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -625,9 +625,12 @@ struct HierarchyPass : public Pass { for (auto module : design->modules()) for (auto cell : module->cells()) { + if (GetSize(cell->parameters) != 0) + continue; + Module *m = design->module(cell->type); - if (m == nullptr) + if (m == nullptr || m->get_bool_attribute("\\blackbox")) continue; for (auto &conn : cell->connections()) diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 6784f48c3..b351d3be8 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -305,10 +305,15 @@ struct TechmapWorker // approach that yields nicer outputs: // replace internal wires that are connected to external wires - if (w->port_output) + if (w->port_output && !w->port_input) { port_signal_map.add(c.second, c.first); - else + } else + if (!w->port_output && w->port_input) { port_signal_map.add(c.first, c.second); + } else { + module->connect(c); + extra_connect = SigSig(); + } for (auto &attr : w->attributes) { if (attr.first == "\\src") |