diff options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/cmds/bugpoint.cc | 1 | ||||
| -rw-r--r-- | passes/cmds/design.cc | 5 | ||||
| -rw-r--r-- | passes/opt/opt_ffinv.cc | 3 | ||||
| -rw-r--r-- | passes/proc/proc_dff.cc | 2 |
4 files changed, 9 insertions, 2 deletions
diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc index e666023fa..c398afffa 100644 --- a/passes/cmds/bugpoint.cc +++ b/passes/cmds/bugpoint.cc @@ -393,6 +393,7 @@ struct BugpointPass : public Pass { } } } + delete design_copy; return nullptr; } diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 169f7cc4a..168d38563 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -118,6 +118,9 @@ struct DesignPass : public Pass { std::string save_name, load_name, as_name, delete_name; std::vector<RTLIL::Module*> copy_src_modules; + if (!design) + log_cmd_error("No default design.\n"); + size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -280,7 +283,7 @@ struct DesignPass : public Pass { done[mod->name] = prefix; } - while (!queue.empty()) + while (!queue.empty() && copy_from_design) { pool<Module*> old_queue; old_queue.swap(queue); diff --git a/passes/opt/opt_ffinv.cc b/passes/opt/opt_ffinv.cc index 5d989dafd..3f7b4bc4a 100644 --- a/passes/opt/opt_ffinv.cc +++ b/passes/opt/opt_ffinv.cc @@ -64,6 +64,7 @@ struct OptFfInvWorker log_assert(d_inv == nullptr); d_inv = port.cell; } + if (!d_inv) return false; if (index.query_is_output(ff.sig_q)) return false; @@ -140,6 +141,7 @@ struct OptFfInvWorker log_assert(d_lut == nullptr); d_lut = port.cell; } + if (!d_lut) return false; if (index.query_is_output(ff.sig_q)) return false; @@ -167,6 +169,7 @@ struct OptFfInvWorker log_assert(q_inv == nullptr); q_inv = port.cell; } + if (!q_inv) return false; ff.flip_rst_bits({0}); ff.sig_q = q_inv->getPort(ID::Y); diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 234671df5..fd56786f2 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -302,7 +302,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) ce.assign_map.apply(rstval); ce.assign_map.apply(sig); - if (rstval == sig) { + if (rstval == sig && sync_level) { if (sync_level->type == RTLIL::SyncType::ST1) insig = mod->Mux(NEW_ID, insig, sig, sync_level->signal); else |