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-rw-r--r--passes/cmds/blackbox.cc2
-rw-r--r--passes/cmds/stat.cc4
-rw-r--r--passes/cmds/write_file.cc2
-rw-r--r--passes/hierarchy/hierarchy.cc38
-rw-r--r--passes/sat/assertpmux.cc6
-rw-r--r--passes/sat/cutpoint.cc2
-rw-r--r--passes/techmap/muxcover.cc6
-rw-r--r--passes/techmap/shregmap.cc2
8 files changed, 51 insertions, 11 deletions
diff --git a/passes/cmds/blackbox.cc b/passes/cmds/blackbox.cc
index 6094f8f16..d09ed872e 100644
--- a/passes/cmds/blackbox.cc
+++ b/passes/cmds/blackbox.cc
@@ -23,7 +23,7 @@ USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct BlackboxPass : public Pass {
- BlackboxPass() : Pass("blackbox", "change type of cells in the design") { }
+ BlackboxPass() : Pass("blackbox", "convert modules into blackbox modules") { }
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc
index d22685b62..27c5fb60c 100644
--- a/passes/cmds/stat.cc
+++ b/passes/cmds/stat.cc
@@ -285,8 +285,8 @@ struct StatPass : public Pass {
log(" use cell area information from the provided liberty file\n");
log("\n");
log(" -tech <technology>\n");
- log(" print area estemate for the specified technology. Corrently supported\n");
- log(" calues for <technology>: xilinx\n");
+ log(" print area estemate for the specified technology. Currently supported\n");
+ log(" values for <technology>: xilinx\n");
log("\n");
log(" -width\n");
log(" annotate internal cell types with their word width.\n");
diff --git a/passes/cmds/write_file.cc b/passes/cmds/write_file.cc
index 9613b462b..64a762d7c 100644
--- a/passes/cmds/write_file.cc
+++ b/passes/cmds/write_file.cc
@@ -62,7 +62,7 @@ struct WriteFileFrontend : public Frontend {
if (argidx < args.size() && args[argidx].rfind("-", 0) != 0)
output_filename = args[argidx++];
else
- log_cmd_error("Missing putput filename.\n");
+ log_cmd_error("Missing output filename.\n");
extra_args(f, filename, args, argidx);
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 24e64a9b2..213437c01 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -591,6 +591,9 @@ struct HierarchyPass : public Pass {
log(" module instances when the width does not match the module port. This\n");
log(" option disables this behavior.\n");
log("\n");
+ log(" -nodefaults\n");
+ log(" do not resolve input port default values\n");
+ log("\n");
log(" -nokeep_asserts\n");
log(" per default this pass sets the \"keep\" attribute on all modules\n");
log(" that directly or indirectly contain one or more formal properties.\n");
@@ -645,6 +648,7 @@ struct HierarchyPass : public Pass {
bool generate_mode = false;
bool keep_positionals = false;
bool keep_portwidths = false;
+ bool nodefaults = false;
bool nokeep_asserts = false;
std::vector<std::string> generate_cells;
std::vector<generate_port_decl_t> generate_ports;
@@ -712,6 +716,10 @@ struct HierarchyPass : public Pass {
keep_portwidths = true;
continue;
}
+ if (args[argidx] == "-nodefaults") {
+ nodefaults = true;
+ continue;
+ }
if (args[argidx] == "-nokeep_asserts") {
nokeep_asserts = true;
continue;
@@ -940,6 +948,36 @@ struct HierarchyPass : public Pass {
}
}
+ if (!nodefaults)
+ {
+ dict<IdString, dict<IdString, Const>> defaults_db;
+
+ for (auto module : design->modules())
+ for (auto wire : module->wires())
+ if (wire->port_input && wire->attributes.count("\\defaultvalue"))
+ defaults_db[module->name][wire->name] = wire->attributes.at("\\defaultvalue");
+
+ for (auto module : design->modules())
+ for (auto cell : module->cells())
+ {
+ if (defaults_db.count(cell->type) == 0)
+ continue;
+
+ if (keep_positionals) {
+ bool found_positionals = false;
+ for (auto &conn : cell->connections())
+ if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9')
+ found_positionals = true;
+ if (found_positionals)
+ continue;
+ }
+
+ for (auto &it : defaults_db.at(cell->type))
+ if (!cell->hasPort(it.first))
+ cell->setPort(it.first, it.second);
+ }
+ }
+
std::set<Module*> blackbox_derivatives;
std::vector<Module*> design_modules = design->modules();
diff --git a/passes/sat/assertpmux.cc b/passes/sat/assertpmux.cc
index 509cb0ba9..3b432c461 100644
--- a/passes/sat/assertpmux.cc
+++ b/passes/sat/assertpmux.cc
@@ -180,7 +180,7 @@ struct AssertpmuxWorker
};
struct AssertpmuxPass : public Pass {
- AssertpmuxPass() : Pass("assertpmux", "convert internal signals to module ports") { }
+ AssertpmuxPass() : Pass("assertpmux", "adds asserts for parallel muxes") { }
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
@@ -195,8 +195,8 @@ struct AssertpmuxPass : public Pass {
log("\n");
log(" -always\n");
log(" usually the $pmux condition is only checked when the $pmux output\n");
- log(" is used be the mux tree it drives. this option will deactivate this\n");
- log(" additional constrained and check the $pmux condition always.\n");
+ log(" is used by the mux tree it drives. this option will deactivate this\n");
+ log(" additional constraint and check the $pmux condition always.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc
index 048aec7f3..b4549bc39 100644
--- a/passes/sat/cutpoint.cc
+++ b/passes/sat/cutpoint.cc
@@ -24,7 +24,7 @@ USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct CutpointPass : public Pass {
- CutpointPass() : Pass("cutpoint", "add hi/lo cover cells for each wire bit") { }
+ CutpointPass() : Pass("cutpoint", "adds formal cut points to the design") { }
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc
index 32102436d..8e44be148 100644
--- a/passes/techmap/muxcover.cc
+++ b/passes/techmap/muxcover.cc
@@ -610,7 +610,7 @@ struct MuxcoverPass : public Pass {
use_mux4 = true;
if (arg.size() > 5) {
if (arg[5] != '=') break;
- cost_mux4 = atoi(arg.substr(5).c_str());
+ cost_mux4 = atoi(arg.substr(6).c_str());
}
continue;
}
@@ -618,7 +618,7 @@ struct MuxcoverPass : public Pass {
use_mux8 = true;
if (arg.size() > 5) {
if (arg[5] != '=') break;
- cost_mux8 = atoi(arg.substr(5).c_str());
+ cost_mux8 = atoi(arg.substr(6).c_str());
}
continue;
}
@@ -626,7 +626,7 @@ struct MuxcoverPass : public Pass {
use_mux16 = true;
if (arg.size() > 6) {
if (arg[6] != '=') break;
- cost_mux16 = atoi(arg.substr(6).c_str());
+ cost_mux16 = atoi(arg.substr(7).c_str());
}
continue;
}
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc
index 21dfe9619..18e60fa6b 100644
--- a/passes/techmap/shregmap.cc
+++ b/passes/techmap/shregmap.cc
@@ -605,9 +605,11 @@ struct ShregmapPass : public Pass {
log("\n");
log(" -tech greenpak4\n");
log(" map to greenpak4 shift registers.\n");
+ log(" this option also implies -clkpol pos -zinit\n");
log("\n");
log(" -tech xilinx\n");
log(" map to xilinx dynamic-length shift registers.\n");
+ log(" this option also implies -params -init\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-31 03:14:15 +0000