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-rw-r--r--passes/tests/test_cell.cc4
1 files changed, 4 insertions, 0 deletions
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index bdb475d3b..228b6b67a 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -264,6 +264,10 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
cell->setPort(ID::Y, wire);
}
+ if (cell_type.in(ID($shiftx))) {
+ cell->parameters[ID::A_SIGNED] = false;
+ }
+
if (cell_type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
cell->parameters[ID::B_SIGNED] = false;
}