diff options
Diffstat (limited to 'passes/techmap')
-rw-r--r-- | passes/techmap/extract.cc | 5 | ||||
-rw-r--r-- | passes/techmap/iopadmap.cc | 9 | ||||
-rw-r--r-- | passes/techmap/techmap.cc | 10 |
3 files changed, 7 insertions, 17 deletions
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index b8c349f5c..92bcafc00 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -729,13 +729,10 @@ struct ExtractPass : public Pass { int portCounter = 1; for (auto wire : wires) { - RTLIL::Wire *newWire = new RTLIL::Wire; - newWire->name = wire->name; - newWire->width = wire->width; + RTLIL::Wire *newWire = newMod->addWire(wire->name, wire->width); newWire->port_id = portCounter++; newWire->port_input = true; newWire->port_output = true; - newMod->add(newWire); } for (auto cell : cells) { diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 114d28e25..ab3bb3ed0 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -164,13 +164,8 @@ struct IopadmapPass : public Pass { log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str()); RTLIL::Wire *new_wire = NULL; - if (!portname2.empty()) { - new_wire = new RTLIL::Wire; - *new_wire = *wire; - wire->name = NEW_ID; - module->wires[wire->name] = wire; - module->wires[new_wire->name] = new_wire; - } + if (!portname2.empty()) + new_wire = module->addWire(NEW_ID, wire); if (flag_bits) { diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 9dcd6a45b..bee1df406 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -128,14 +128,14 @@ struct TechmapWorker for (auto &it : tpl->wires) { if (it.second->port_id > 0) positional_ports[stringf("$%d", it.second->port_id)] = it.first; - RTLIL::Wire *w = new RTLIL::Wire(*it.second); - apply_prefix(cell->name, w->name); + std::string w_name = it.second->name; + apply_prefix(cell->name, w_name); + RTLIL::Wire *w = module->addWire(w_name, it.second); w->port_input = false; w->port_output = false; w->port_id = 0; if (it.second->get_bool_attribute("\\_techmap_special_")) w->attributes.clear(); - module->add(w); design->select(module, w); } @@ -381,7 +381,6 @@ struct TechmapWorker log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value)); techmap_wire_names.erase(it.first); - tpl->wires.erase(data.wire->name); const char *p = data.wire->name.c_str(); const char *q = strrchr(p+1, '.'); @@ -391,8 +390,7 @@ struct TechmapWorker std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12); while (tpl->wires.count(new_name)) new_name += "_"; - data.wire->name = new_name; - tpl->add(data.wire); + tpl->rename(data.wire, new_name); std::string cmd_string = data.value.as_const().decode_string(); Pass::call_on_module(map, tpl, cmd_string); |