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-rw-r--r--passes/techmap/abc.cc2
-rw-r--r--passes/techmap/abc9.cc2
2 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index ff98a6e36..61ee99ee7 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -780,7 +780,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
if (dff_mode && clk_sig.empty())
log_cmd_error("Clock domain %s not found.\n", clk_str.c_str());
- std::string tempdir_name = "/tmp/" + proc_program_prefix()+ "yosys-abc-XXXXXX";
+ std::string tempdir_name = get_base_tmpdir() + "/" + proc_program_prefix()+ "yosys-abc-XXXXXX";
if (!cleanup)
tempdir_name[0] = tempdir_name[4] = '_';
tempdir_name = make_temp_dir(tempdir_name);
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index fe0802d70..79c994b11 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -404,7 +404,7 @@ struct Abc9Pass : public ScriptPass
if (!active_design->selected_whole_module(mod))
log_error("Can't handle partially selected module %s!\n", log_id(mod));
- std::string tempdir_name = "/tmp/" + proc_program_prefix() + "yosys-abc-XXXXXX";
+ std::string tempdir_name = get_base_tmpdir() + "/" + proc_program_prefix() + "yosys-abc-XXXXXX";
if (!cleanup)
tempdir_name[0] = tempdir_name[4] = '_';
tempdir_name = make_temp_dir(tempdir_name);