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-rw-r--r--passes/techmap/techmap.cc64
1 files changed, 32 insertions, 32 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index cf283002a..e81dc33ee 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -145,8 +145,8 @@ struct TechmapWorker
record.wire = it.second;
record.value = it.second;
result[p].push_back(record);
- it.second->attributes[ID(\\keep)] = RTLIL::Const(1);
- it.second->attributes[ID(\\_techmap_special_)] = RTLIL::Const(1);
+ it.second->attributes[ID(keep)] = RTLIL::Const(1);
+ it.second->attributes[ID(_techmap_special_)] = RTLIL::Const(1);
}
}
@@ -175,11 +175,11 @@ struct TechmapWorker
}
std::string orig_cell_name;
- pool<string> extra_src_attrs = cell->get_strpool_attribute(ID(\\src));
+ pool<string> extra_src_attrs = cell->get_strpool_attribute(ID(src));
if (!flatten_mode) {
for (auto &it : tpl->cells_)
- if (it.first == ID(\\_TECHMAP_REPLACE_)) {
+ if (it.first == ID(_TECHMAP_REPLACE_)) {
orig_cell_name = cell->name.str();
module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
break;
@@ -197,8 +197,8 @@ struct TechmapWorker
m->start_offset = it.second->start_offset;
m->size = it.second->size;
m->attributes = it.second->attributes;
- if (m->attributes.count(ID(\\src)))
- m->add_strpool_attribute(ID(\\src), extra_src_attrs);
+ if (m->attributes.count(ID(src)))
+ m->add_strpool_attribute(ID(src), extra_src_attrs);
module->memories[m->name] = m;
memory_renames[it.first] = m->name;
design->select(module, m);
@@ -215,10 +215,10 @@ struct TechmapWorker
w->port_input = false;
w->port_output = false;
w->port_id = 0;
- if (it.second->get_bool_attribute(ID(\\_techmap_special_)))
+ if (it.second->get_bool_attribute(ID(_techmap_special_)))
w->attributes.clear();
- if (w->attributes.count(ID(\\src)))
- w->add_strpool_attribute(ID(\\src), extra_src_attrs);
+ if (w->attributes.count(ID(src)))
+ w->add_strpool_attribute(ID(src), extra_src_attrs);
design->select(module, w);
}
@@ -320,7 +320,7 @@ struct TechmapWorker
}
for (auto &attr : w->attributes) {
- if (attr.first == ID(\\src))
+ if (attr.first == ID(src))
continue;
module->connect(extra_connect);
break;
@@ -331,7 +331,7 @@ struct TechmapWorker
for (auto &it : tpl->cells_)
{
IdString c_name = it.second->name.str();
- bool techmap_replace_cell = (!flatten_mode) && (c_name == ID(\\_TECHMAP_REPLACE_));
+ bool techmap_replace_cell = (!flatten_mode) && (c_name == ID(_TECHMAP_REPLACE_));
if (techmap_replace_cell)
c_name = orig_cell_name;
@@ -350,19 +350,19 @@ struct TechmapWorker
}
if (c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
- IdString memid = c->getParam(ID(\\MEMID)).decode_string();
+ IdString memid = c->getParam(ID(MEMID)).decode_string();
log_assert(memory_renames.count(memid) != 0);
- c->setParam(ID(\\MEMID), Const(memory_renames[memid].str()));
+ c->setParam(ID(MEMID), Const(memory_renames[memid].str()));
}
if (c->type == ID($mem)) {
- IdString memid = c->getParam(ID(\\MEMID)).decode_string();
+ IdString memid = c->getParam(ID(MEMID)).decode_string();
apply_prefix(cell->name, memid);
- c->setParam(ID(\\MEMID), Const(memid.c_str()));
+ c->setParam(ID(MEMID), Const(memid.c_str()));
}
- if (c->attributes.count(ID(\\src)))
- c->add_strpool_attribute(ID(\\src), extra_src_attrs);
+ if (c->attributes.count(ID(src)))
+ c->add_strpool_attribute(ID(src), extra_src_attrs);
if (techmap_replace_cell)
for (auto attr : cell->attributes)
@@ -416,9 +416,9 @@ struct TechmapWorker
}
if (flatten_mode) {
- bool keepit = cell->get_bool_attribute(ID(\\keep_hierarchy));
+ bool keepit = cell->get_bool_attribute(ID(keep_hierarchy));
for (auto &tpl_name : celltypeMap.at(cell_type))
- if (map->modules_[tpl_name]->get_bool_attribute(ID(\\keep_hierarchy)))
+ if (map->modules_[tpl_name]->get_bool_attribute(ID(keep_hierarchy)))
keepit = true;
if (keepit) {
if (!flatten_keep_list[cell]) {
@@ -484,13 +484,13 @@ struct TechmapWorker
{
std::string extmapper_name;
- if (tpl->get_bool_attribute(ID(\\techmap_simplemap)))
+ if (tpl->get_bool_attribute(ID(techmap_simplemap)))
extmapper_name = "simplemap";
- if (tpl->get_bool_attribute(ID(\\techmap_maccmap)))
+ if (tpl->get_bool_attribute(ID(techmap_maccmap)))
extmapper_name = "maccmap";
- if (tpl->attributes.count(ID(\\techmap_wrap)))
+ if (tpl->attributes.count(ID(techmap_wrap)))
extmapper_name = "wrap";
if (!extmapper_name.empty())
@@ -505,7 +505,7 @@ struct TechmapWorker
m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
if (extmapper_name == "wrap")
- m_name += ":" + sha1(tpl->attributes.at(ID(\\techmap_wrap)).decode_string());
+ m_name += ":" + sha1(tpl->attributes.at(ID(techmap_wrap)).decode_string());
RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
@@ -520,7 +520,7 @@ struct TechmapWorker
int port_counter = 1;
for (auto &c : extmapper_cell->connections_) {
RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
- if (w->name.in(ID(\\Y), ID(\\Q)))
+ if (w->name.in(ID(Y), ID(Q)))
w->port_output = true;
else
w->port_input = true;
@@ -548,7 +548,7 @@ struct TechmapWorker
}
if (extmapper_name == "wrap") {
- std::string cmd_string = tpl->attributes.at(ID(\\techmap_wrap)).decode_string();
+ std::string cmd_string = tpl->attributes.at(ID(techmap_wrap)).decode_string();
log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
mkdebug.on();
Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
@@ -616,8 +616,8 @@ struct TechmapWorker
continue;
}
- if (tpl->avail_parameters.count(ID(\\_TECHMAP_CELLTYPE_)) != 0)
- parameters[ID(\\_TECHMAP_CELLTYPE_)] = RTLIL::unescape_id(cell->type);
+ if (tpl->avail_parameters.count(ID(_TECHMAP_CELLTYPE_)) != 0)
+ parameters[ID(_TECHMAP_CELLTYPE_)] = RTLIL::unescape_id(cell->type);
for (auto conn : cell->connections()) {
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) {
@@ -656,8 +656,8 @@ struct TechmapWorker
bits = i;
// Increment index by one to get number of bits
bits++;
- if (tpl->avail_parameters.count(ID(\\_TECHMAP_BITS_CONNMAP_)))
- parameters[ID(\\_TECHMAP_BITS_CONNMAP_)] = bits;
+ if (tpl->avail_parameters.count(ID(_TECHMAP_BITS_CONNMAP_)))
+ parameters[ID(_TECHMAP_BITS_CONNMAP_)] = bits;
for (auto conn : cell->connections())
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
@@ -1136,8 +1136,8 @@ struct TechmapPass : public Pass {
std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
for (auto &it : map->modules_) {
- if (it.second->attributes.count(ID(\\techmap_celltype)) && !it.second->attributes.at(ID(\\techmap_celltype)).bits.empty()) {
- char *p = strdup(it.second->attributes.at(ID(\\techmap_celltype)).decode_string().c_str());
+ if (it.second->attributes.count(ID(techmap_celltype)) && !it.second->attributes.at(ID(techmap_celltype)).bits.empty()) {
+ char *p = strdup(it.second->attributes.at(ID(techmap_celltype)).decode_string().c_str());
for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
celltypeMap[RTLIL::escape_id(q)].insert(it.first);
free(p);
@@ -1222,7 +1222,7 @@ struct FlattenPass : public Pass {
RTLIL::Module *top_mod = NULL;
if (design->full_selection())
for (auto mod : design->modules())
- if (mod->get_bool_attribute(ID(\\top)))
+ if (mod->get_bool_attribute(ID(top)))
top_mod = mod;
std::set<RTLIL::Cell*> handled_cells;
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 06:02:58 +0000