static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref, bool &polarity)

{

return false;

if (signal == ref)

return true;

polarity = !polarity;

}

polarity = !polarity;

}

polarity = !polarity;

}

polarity = !polarity;

}

}

polarity = !polarity;

}

polarity = !polarity;

}

}

}

{

for (auto &action : cs->actions) {

if (unknown)

else

rspec.replace(action.first, action.second, &rval);

}

for (auto sw : cs->switches) {

for (auto cs2 : sw->cases)

apply_const(mod, rspec, rval, cs2, const_sig, polarity, unknown);

}

if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) {

bool polarity = sync->type == RTLIL::SyncType::STp;

if (check_signal(mod, root_sig, sync->signal, polarity)) {

for (auto &action : sync->actions) {

RTLIL::SigSpec rspec = action.second;

RTLIL::SigSpec last_rval;

for (int count = 0; rval != last_rval; count++) {

last_rval = rval;

extra_args(args, argidx, design);

continue;

continue;

std::vector<RTLIL::SigSig> arst_actions;

for (auto sync : proc_it.second->syncs)

if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn)

for (auto &act : sync->actions) {

RTLIL::SigSpec arst_sig, arst_val;

if (chunk.wire && chunk.wire->attributes.count("\\init")) {

RTLIL::SigSpec value = chunk.wire->attributes.at("\\init");

value.extend(chunk.wire->width, false);

arst_sig.append(chunk);

arst_val.append(value.extract(chunk.offset, chunk.width));

}

log("Added global reset to process %s: %s <- %s\n",

proc_it.first.c_str(), log_signal(arst_sig), log_signal(arst_val));

arst_actions.push_back(RTLIL::SigSig(arst_sig, arst_val));

if (!arst_actions.empty()) {

RTLIL::SyncRule *sync = new RTLIL::SyncRule;

sync->type = global_arst_neg ? RTLIL::SyncType::ST0 : RTLIL::SyncType::ST1;

sync->actions = arst_actions;

proc_it.second->syncs.push_back(sync);

}

void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did_something, int &count, int max_depth)

{

{

int found_matching_case_idx = -1;

for (int i = 0; i < int(sw->cases.size()) && found_matching_case_idx < 0; i++)

sw->signal = RTLIL::SigSpec();

}

{

did_something = true;

for (auto &action : sw->cases[0]->actions)

void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count, int max_depth)

{

for (size_t i = 0; i < cs->actions.size(); i++) {

did_something = true;

cs->actions.erase(cs->actions.begin() + (i--));

}

bool did_something = true;

for (size_t i = 0; i < proc->syncs.size(); i++) {

for (size_t j = 0; j < proc->syncs[i]->actions.size(); j++)

proc->syncs[i]->actions.erase(proc->syncs[i]->actions.begin() + (j--));

if (proc->syncs[i]->actions.size() == 0) {

delete proc->syncs[i];

extra_args(args, 1, design);

continue;

continue;

if (proc_it.second->syncs.size() == 0 && proc_it.second->root_case.switches.size() == 0 &&

proc_it.second->root_case.actions.size() == 0) {

delme.push_back(proc_it.first);

}

}

for (auto &id : delme) {

}

}

#include <sstream>

#include <stdlib.h>

#include <stdio.h>

static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc)

{

for (auto sync : proc->syncs)

for (auto &action : sync->actions)

lvalue = action.first;

lvalue.sort_and_unify();

break;

this_lvalue.append(action.first);

this_lvalue.sort_and_unify();

RTLIL::SigSpec common_sig = this_lvalue.extract(lvalue);

lvalue = common_sig;

}

static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::SigSpec clk, bool clk_polarity,

std::map<RTLIL::SigSpec, std::set<RTLIL::SyncRule*>> &async_rules, RTLIL::Process *proc)

{

for (auto &it : async_rules)

{

else

log_abort();

cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);

cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);

}

cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);

cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);

}

cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);

cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);

}

inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);

}

std::stringstream sstr;

cell->attributes = proc->attributes;

cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);

cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1);

cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1);

log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",

cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");

bool clk_polarity, bool set_polarity, RTLIL::SigSpec clk, RTLIL::SigSpec set, RTLIL::Process *proc)

{

std::stringstream sstr;

inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0);

cell->attributes = proc->attributes;

cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);

cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1);

cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1);

log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(),

clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative");

bool clk_polarity, bool arst_polarity, RTLIL::SigSpec clk, RTLIL::SigSpec *arst, RTLIL::Process *proc)

{

std::stringstream sstr;

cell->attributes = proc->attributes;

if (arst) {

cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity, 1);

cell->parameters["\\ARST_VALUE"] = val_rst;

}

cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);

if (arst)

log(" created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");

if (arst)

RTLIL::SigSpec sig = find_any_lvalue(proc);

bool free_sync_level = false;

break;

log("Creating register for signal `%s.%s' using process `%s.%s'.\n",

mod->name.c_str(), log_signal(sig), mod->name.c_str(), proc->name.c_str());

RTLIL::SyncRule *sync_level = NULL;

RTLIL::SyncRule *sync_edge = NULL;

RTLIL::SyncRule *sync_always = NULL;

for (auto sync : proc->syncs)

for (auto &action : sync->actions)

{

continue;

if (sync->type == RTLIL::SyncType::ST0 || sync->type == RTLIL::SyncType::ST1) {

if (sync_level != NULL && sync_level != sync) {

// log_error("Multiple level sensitive events found for this signal!\n");

many_async_rules[rstval].insert(sync_level);

}

sig.replace(action.first, action.second, &rstval);

sync_level = sync;

}

{

sync_level = new RTLIL::SyncRule;

sync_level->type = RTLIL::SyncType::ST1;

sync_level->actions.push_back(RTLIL::SigSig(sig, rstval));

free_sync_level = true;

inputs.append(it->signal);

compare.append(it->type == RTLIL::SyncType::ST0 ? RTLIL::State::S1 : RTLIL::State::S0);

}

cell->parameters["\\A_SIGNED"] = RTLIL::Const(false, 1);

cell->parameters["\\B_SIGNED"] = RTLIL::Const(false, 1);

cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);

many_async_rules.clear();

}

else

{

sync_level = NULL;

}

}

ce.assign_map.apply(rstval);

ce.assign_map.apply(sig);

if (sync_always) {

if (sync_edge || sync_level || many_async_rules.size() > 0)

log_error("Mixed always event with edge and/or level sensitive events!\n");

log(" created direct connection (no actual register cell created).\n");

continue;

}

sync_edge->signal, sync_level->signal, proc);

}

else

sync_edge->type == RTLIL::SyncType::STp,

sync_level && sync_level->type == RTLIL::SyncType::ST1,

sync_edge->signal, sync_level ? &sync_level->signal : NULL, proc);

extra_args(args, 1, design);

}

}

} ProcDffPass;

static void proc_get_const(RTLIL::SigSpec &sig, RTLIL::CaseRule &rule)

{

while (1) {

RTLIL::SigSpec tmp = sig;

for (auto &it : rule.actions)

tmp.replace(it.first, it.second);

RTLIL::SigSpec lhs = action.first;

RTLIL::SigSpec rhs = action.second;

proc_get_const(rhs, proc->root_case);

if (!rhs.is_fully_const())

log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs));

int offset = 0;

}

}

}

extra_args(args, 1, design);

}

} ProcInitPass;

#include <sstream>

#include <stdlib.h>

#include <stdio.h>

static RTLIL::SigSpec find_any_lvalue(const RTLIL::CaseRule *cs)

{

for (auto &action : cs->actions) {

return action.first;

}

for (auto sw : cs->switches)

for (auto cs2 : sw->cases) {

RTLIL::SigSpec sig = find_any_lvalue(cs2);

return sig;

}

{

for (auto &action : cs->actions) {

RTLIL::SigSpec lvalue = action.first.extract(sig);

sig = lvalue;

}

static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SwitchRule *sw)

{

std::stringstream sstr;

for (auto comp : compare)

{

RTLIL::SigSpec sig = signal;

// get rid of don't-care bits

}

return RTLIL::SigSpec();

{

}

else

{

// create compare cell

eq_cell->attributes = sw->attributes;

eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);

eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(0);

eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);

}

}

}

else

{

// reduce cmp vector to one logic signal

any_cell->attributes = sw->attributes;

any_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);

any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width);

any_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);

}

return RTLIL::SigSpec(ctrl_wire);

static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw)

{

std::stringstream sstr;

// the trivial cases

if (compare.size() == 0 || when_signal == else_signal)

// compare results

RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw);

return when_signal;

// prepare multiplexer output signal

// create the multiplexer itself

mux_cell->attributes = sw->attributes;

last_mux_cell = mux_cell;

return RTLIL::SigSpec(result_wire);

static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw)

{

RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw);

last_mux_cell->type = "$pmux";

}

static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval)

// detect groups of parallel cases

std::vector<int> pgroups(sw->cases.size());

if (!sw->get_bool_attribute("\\parallel_case")) {

bool extra_group_for_next_case = false;

for (size_t i = 0; i < sw->cases.size(); i++) {

RTLIL::CaseRule *cs2 = sw->cases[i];

if (cs2->compare.empty())

pgroups[i] = pgroups[i-1]+1;

if (pgroups[i] != pgroups[i-1])

}

for (auto pat : cs2->compare)

if (!pat.is_fully_const())

{

RTLIL::SigSpec sig = find_any_lvalue(&proc->root_case);

break;

if (first) {

log(" creating decoder for signal `%s'.\n", log_signal(sig));

}

}

extra_args(args, 1, design);

}

} ProcMuxPass;

#include <sstream>

#include <stdlib.h>

#include <stdio.h>

#include <set>

static void proc_rmdead(RTLIL::SwitchRule *sw, int &counter)

for (size_t i = 0; i < sw->cases.size(); i++)

{

for (size_t j = 0; j < sw->cases[i]->compare.size(); j++) {

RTLIL::SigSpec sig = sw->cases[i]->compare[j];

extra_args(args, 1, design);

int total_counter = 0;

continue;

continue;

int counter = 0;

for (auto switch_it : proc_it.second->root_case.switches)

proc_rmdead(switch_it, counter);

if (counter > 0)

log("Removed %d dead cases from process %s in module %s.\n", counter,

total_counter += counter;

}

}