diff options
Diffstat (limited to 'passes/proc')
-rw-r--r-- | passes/proc/proc_arst.cc | 18 | ||||
-rw-r--r-- | passes/proc/proc_clean.cc | 8 | ||||
-rw-r--r-- | passes/proc/proc_dff.cc | 82 | ||||
-rw-r--r-- | passes/proc/proc_init.cc | 12 | ||||
-rw-r--r-- | passes/proc/proc_mux.cc | 44 |
5 files changed, 82 insertions, 82 deletions
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index a773e5e72..b5763508a 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -28,7 +28,7 @@ extern void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref, bool &polarity) { - if (signal.__width != 1) + if (signal.size() != 1) return false; if (signal == ref) return true; @@ -80,13 +80,13 @@ static void apply_const(RTLIL::Module *mod, const RTLIL::SigSpec rspec, RTLIL::S { for (auto &action : cs->actions) { if (unknown) - rspec.replace(action.first, RTLIL::SigSpec(RTLIL::State::Sm, action.second.__width), &rval); + rspec.replace(action.first, RTLIL::SigSpec(RTLIL::State::Sm, action.second.size()), &rval); else rspec.replace(action.first, action.second, &rval); } for (auto sw : cs->switches) { - if (sw->signal.__width == 0) { + if (sw->signal.size() == 0) { for (auto cs2 : sw->cases) apply_const(mod, rspec, rval, cs2, const_sig, polarity, unknown); } @@ -164,11 +164,11 @@ restart_proc_arst: } for (auto &action : sync->actions) { RTLIL::SigSpec rspec = action.second; - RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.__width); + RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.size()); rspec.expand(), rval.expand(); - for (int i = 0; i < int(rspec.__chunks.size()); i++) - if (rspec.__chunks[i].wire == NULL) - rval.__chunks[i] = rspec.__chunks[i]; + for (int i = 0; i < int(rspec.chunks().size()); i++) + if (rspec.chunks()[i].wire == NULL) + rval.chunks()[i] = rspec.chunks()[i]; rspec.optimize(), rval.optimize(); RTLIL::SigSpec last_rval; for (int count = 0; rval != last_rval; count++) { @@ -252,14 +252,14 @@ struct ProcArstPass : public Pass { if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) for (auto &act : sync->actions) { RTLIL::SigSpec arst_sig, arst_val; - for (auto &chunk : act.first.__chunks) + for (auto &chunk : act.first.chunks()) if (chunk.wire && chunk.wire->attributes.count("\\init")) { RTLIL::SigSpec value = chunk.wire->attributes.at("\\init"); value.extend(chunk.wire->width, false); arst_sig.append(chunk); arst_val.append(value.extract(chunk.offset, chunk.width)); } - if (arst_sig.__width) { + if (arst_sig.size()) { log("Added global reset to process %s: %s <- %s\n", proc_it.first.c_str(), log_signal(arst_sig), log_signal(arst_val)); arst_actions.push_back(RTLIL::SigSig(arst_sig, arst_val)); diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 768660686..682515c5e 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -27,7 +27,7 @@ extern void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did_something, int &count, int max_depth) { - if (sw->signal.__width > 0 && sw->signal.is_fully_const()) + if (sw->signal.size() > 0 && sw->signal.is_fully_const()) { int found_matching_case_idx = -1; for (int i = 0; i < int(sw->cases.size()) && found_matching_case_idx < 0; i++) @@ -59,7 +59,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did sw->signal = RTLIL::SigSpec(); } - if (sw->cases.size() == 1 && (sw->signal.__width == 0 || sw->cases[0]->compare.empty())) + if (sw->cases.size() == 1 && (sw->signal.size() == 0 || sw->cases[0]->compare.empty())) { did_something = true; for (auto &action : sw->cases[0]->actions) @@ -91,7 +91,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count, int max_depth) { for (size_t i = 0; i < cs->actions.size(); i++) { - if (cs->actions[i].first.__width == 0) { + if (cs->actions[i].first.size() == 0) { did_something = true; cs->actions.erase(cs->actions.begin() + (i--)); } @@ -114,7 +114,7 @@ static void proc_clean(RTLIL::Module *mod, RTLIL::Process *proc, int &total_coun bool did_something = true; for (size_t i = 0; i < proc->syncs.size(); i++) { for (size_t j = 0; j < proc->syncs[i]->actions.size(); j++) - if (proc->syncs[i]->actions[j].first.__width == 0) + if (proc->syncs[i]->actions[j].first.size() == 0) proc->syncs[i]->actions.erase(proc->syncs[i]->actions.begin() + (j--)); if (proc->syncs[i]->actions.size() == 0) { delete proc->syncs[i]; diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index d3dff8efc..8e5fbe8f4 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -32,7 +32,7 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) for (auto sync : proc->syncs) for (auto &action : sync->actions) - if (action.first.__width > 0) { + if (action.first.size() > 0) { lvalue = action.first; lvalue.sort_and_unify(); break; @@ -44,7 +44,7 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) this_lvalue.append(action.first); this_lvalue.sort_and_unify(); RTLIL::SigSpec common_sig = this_lvalue.extract(lvalue); - if (common_sig.__width > 0) + if (common_sig.size() > 0) lvalue = common_sig; } @@ -54,8 +54,8 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::SigSpec clk, bool clk_polarity, std::map<RTLIL::SigSpec, std::set<RTLIL::SyncRule*>> &async_rules, RTLIL::Process *proc) { - RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.__width); - RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sig_d.__width); + RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.size()); + RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sig_d.size()); for (auto &it : async_rules) { @@ -72,24 +72,24 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S else log_abort(); - if (sync_low_signals.__width > 1) { + if (sync_low_signals.size() > 1) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$reduce_or"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.__width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_low_signals; cell->connections["\\Y"] = sync_low_signals = mod->addWire(NEW_ID); mod->add(cell); } - if (sync_low_signals.__width > 0) { + if (sync_low_signals.size() > 0) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$not"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.__width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_low_signals; cell->connections["\\Y"] = mod->addWire(NEW_ID); @@ -97,12 +97,12 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S mod->add(cell); } - if (sync_high_signals.__width > 1) { + if (sync_high_signals.size() > 1) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$reduce_or"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.__width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_high_signals; cell->connections["\\Y"] = sync_high_signals = mod->addWire(NEW_ID); @@ -113,30 +113,30 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S inv_cell->name = NEW_ID; inv_cell->type = "$not"; inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.__width); - inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.__width); + inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size()); + inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size()); inv_cell->connections["\\A"] = sync_value; - inv_cell->connections["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.__width); + inv_cell->connections["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.size()); mod->add(inv_cell); RTLIL::Cell *mux_set_cell = new RTLIL::Cell; mux_set_cell->name = NEW_ID; mux_set_cell->type = "$mux"; - mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.__width); + mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); mux_set_cell->connections["\\A"] = sig_sr_set; mux_set_cell->connections["\\B"] = sync_value; mux_set_cell->connections["\\S"] = sync_high_signals; - mux_set_cell->connections["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.__width); + mux_set_cell->connections["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.size()); mod->add(mux_set_cell); RTLIL::Cell *mux_clr_cell = new RTLIL::Cell; mux_clr_cell->name = NEW_ID; mux_clr_cell->type = "$mux"; - mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.__width); + mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); mux_clr_cell->connections["\\A"] = sig_sr_clr; mux_clr_cell->connections["\\B"] = sync_value_inv; mux_clr_cell->connections["\\S"] = sync_high_signals; - mux_clr_cell->connections["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.__width); + mux_clr_cell->connections["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()); mod->add(mux_clr_cell); } @@ -147,7 +147,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->name = sstr.str(); cell->type = "$dffsr"; cell->attributes = proc->attributes; - cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.__width); + cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); @@ -168,16 +168,16 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec std::stringstream sstr; sstr << "$procdff$" << (RTLIL::autoidx++); - RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.__width); - RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.__width); - RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.__width); + RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.size()); + RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.size()); + RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.size()); RTLIL::Cell *inv_set = new RTLIL::Cell; inv_set->name = NEW_ID; inv_set->type = "$not"; inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0); - inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.__width); - inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.__width); + inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size()); + inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size()); inv_set->connections["\\A"] = sig_set; inv_set->connections["\\Y"] = sig_set_inv; mod->add(inv_set); @@ -185,8 +185,8 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec RTLIL::Cell *mux_sr_set = new RTLIL::Cell; mux_sr_set->name = NEW_ID; mux_sr_set->type = "$mux"; - mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); - mux_sr_set->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.__width); + mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); + mux_sr_set->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); mux_sr_set->connections[set_polarity ? "\\B" : "\\A"] = sig_set; mux_sr_set->connections["\\Y"] = sig_sr_set; mux_sr_set->connections["\\S"] = set; @@ -195,8 +195,8 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec RTLIL::Cell *mux_sr_clr = new RTLIL::Cell; mux_sr_clr->name = NEW_ID; mux_sr_clr->type = "$mux"; - mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); - mux_sr_clr->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.__width); + mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); + mux_sr_clr->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); mux_sr_clr->connections[set_polarity ? "\\B" : "\\A"] = sig_set_inv; mux_sr_clr->connections["\\Y"] = sig_sr_clr; mux_sr_clr->connections["\\S"] = set; @@ -206,7 +206,7 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec cell->name = sstr.str(); cell->type = "$dffsr"; cell->attributes = proc->attributes; - cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); + cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); @@ -233,7 +233,7 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_ cell->attributes = proc->attributes; mod->cells[cell->name] = cell; - cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); + cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); if (arst) { cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity, 1); cell->parameters["\\ARST_VALUE"] = val_rst; @@ -259,14 +259,14 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) RTLIL::SigSpec sig = find_any_lvalue(proc); bool free_sync_level = false; - if (sig.__width == 0) + if (sig.size() == 0) break; log("Creating register for signal `%s.%s' using process `%s.%s'.\n", mod->name.c_str(), log_signal(sig), mod->name.c_str(), proc->name.c_str()); - RTLIL::SigSpec insig = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); - RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); + RTLIL::SigSpec insig = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); + RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); RTLIL::SyncRule *sync_level = NULL; RTLIL::SyncRule *sync_edge = NULL; RTLIL::SyncRule *sync_always = NULL; @@ -276,16 +276,16 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) for (auto sync : proc->syncs) for (auto &action : sync->actions) { - if (action.first.extract(sig).__width == 0) + if (action.first.extract(sig).size() == 0) continue; if (sync->type == RTLIL::SyncType::ST0 || sync->type == RTLIL::SyncType::ST1) { if (sync_level != NULL && sync_level != sync) { // log_error("Multiple level sensitive events found for this signal!\n"); many_async_rules[rstval].insert(sync_level); - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); } - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); sig.replace(action.first, action.second, &rstval); sync_level = sync; } @@ -324,15 +324,15 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) inputs.append(it->signal); compare.append(it->type == RTLIL::SyncType::ST0 ? RTLIL::State::S1 : RTLIL::State::S0); } - assert(inputs.__width == compare.__width); + assert(inputs.size() == compare.size()); RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$ne"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(false, 1); cell->parameters["\\B_SIGNED"] = RTLIL::Const(false, 1); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.__width); - cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.__width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size()); + cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = inputs; cell->connections["\\B"] = compare; @@ -343,7 +343,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) } else { - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); sync_level = NULL; } } @@ -357,7 +357,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) sig.optimize(); if (rstval == sig) { - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); sync_level = NULL; } @@ -386,7 +386,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) sync_edge->signal, sync_level->signal, proc); } else - gen_dff(mod, insig, rstval.__chunks[0].data, sig, + gen_dff(mod, insig, rstval.chunks()[0].data, sig, sync_edge->type == RTLIL::SyncType::STp, sync_level && sync_level->type == RTLIL::SyncType::ST1, sync_edge->signal, sync_level ? &sync_level->signal : NULL, proc); diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 0ef17b22d..ba1fb5ab9 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -60,13 +60,13 @@ static void proc_init(RTLIL::Module *mod, RTLIL::Process *proc) log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs)); int offset = 0; - for (size_t i = 0; i < lhs.__chunks.size(); i++) { - if (lhs.__chunks[i].wire == NULL) + for (size_t i = 0; i < lhs.chunks().size(); i++) { + if (lhs.chunks()[i].wire == NULL) continue; - RTLIL::Wire *wire = lhs.__chunks[i].wire; - RTLIL::SigSpec value = rhs.extract(offset, lhs.__chunks[i].width); - if (value.__width != wire->width) - log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs.__chunks[i]), log_signal(value)); + RTLIL::Wire *wire = lhs.chunks()[i].wire; + RTLIL::SigSpec value = rhs.extract(offset, lhs.chunks()[i].width); + if (value.size() != wire->width) + log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs.chunks()[i]), log_signal(value)); log(" Setting init value: %s = %s\n", log_signal(wire), log_signal(value)); wire->attributes["\\init"] = value.as_const(); offset += wire->width; diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 2e24e786b..cd459d949 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -28,14 +28,14 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::CaseRule *cs) { for (auto &action : cs->actions) { - if (action.first.__width) + if (action.first.size()) return action.first; } for (auto sw : cs->switches) for (auto cs2 : sw->cases) { RTLIL::SigSpec sig = find_any_lvalue(cs2); - if (sig.__width) + if (sig.size()) return sig; } @@ -46,7 +46,7 @@ static void extract_core_signal(const RTLIL::CaseRule *cs, RTLIL::SigSpec &sig) { for (auto &action : cs->actions) { RTLIL::SigSpec lvalue = action.first.extract(sig); - if (lvalue.__width) + if (lvalue.size()) sig = lvalue; } @@ -72,18 +72,18 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, comp.expand(); // get rid of don't-care bits - assert(sig.__width == comp.__width); - for (int i = 0; i < comp.__width; i++) - if (comp.__chunks[i].wire == NULL && comp.__chunks[i].data.bits[0] == RTLIL::State::Sa) { + assert(sig.size() == comp.size()); + for (int i = 0; i < comp.size(); i++) + if (comp.chunks()[i].wire == NULL && comp.chunks()[i].data.bits[0] == RTLIL::State::Sa) { sig.remove(i, 1); comp.remove(i--, 1); } - if (comp.__width == 0) + if (comp.size() == 0) return RTLIL::SigSpec(); sig.optimize(); comp.optimize(); - if (sig.__width == 1 && comp == RTLIL::SigSpec(1,1)) + if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1)) { mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, 1, cmp_wire->width++), sig)); } @@ -101,8 +101,8 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(0); - eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.__width); - eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.__width); + eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size()); + eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size()); eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); eq_cell->connections["\\A"] = sig; @@ -143,7 +143,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw) { - assert(when_signal.__width == else_signal.__width); + assert(when_signal.size() == else_signal.size()); std::stringstream sstr; sstr << "$procmux$" << (RTLIL::autoidx++); @@ -154,14 +154,14 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, // compare results RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); - if (ctrl_sig.__width == 0) + if (ctrl_sig.size() == 0) return when_signal; - assert(ctrl_sig.__width == 1); + assert(ctrl_sig.size() == 1); // prepare multiplexer output signal RTLIL::Wire *result_wire = new RTLIL::Wire; result_wire->name = sstr.str() + "_Y"; - result_wire->width = when_signal.__width; + result_wire->width = when_signal.size(); mod->wires[result_wire->name] = result_wire; // create the multiplexer itself @@ -171,7 +171,7 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, mux_cell->attributes = sw->attributes; mod->cells[mux_cell->name] = mux_cell; - mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.__width); + mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size()); mux_cell->connections["\\A"] = else_signal; mux_cell->connections["\\B"] = when_signal; mux_cell->connections["\\S"] = ctrl_sig; @@ -184,14 +184,14 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw) { assert(last_mux_cell != NULL); - assert(when_signal.__width == last_mux_cell->connections["\\A"].__width); + assert(when_signal.size() == last_mux_cell->connections["\\A"].size()); RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); - assert(ctrl_sig.__width == 1); + assert(ctrl_sig.size() == 1); last_mux_cell->type = "$pmux"; last_mux_cell->connections["\\S"].append(ctrl_sig); last_mux_cell->connections["\\B"].append(when_signal); - last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections["\\S"].__width; + last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections["\\S"].size(); } static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval) @@ -208,7 +208,7 @@ static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs // detect groups of parallel cases std::vector<int> pgroups(sw->cases.size()); if (!sw->get_bool_attribute("\\parallel_case")) { - BitPatternPool pool(sw->signal.__width); + BitPatternPool pool(sw->signal.size()); bool extra_group_for_next_case = false; for (size_t i = 0; i < sw->cases.size(); i++) { RTLIL::CaseRule *cs2 = sw->cases[i]; @@ -224,7 +224,7 @@ static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs if (cs2->compare.empty()) pgroups[i] = pgroups[i-1]+1; if (pgroups[i] != pgroups[i-1]) - pool = BitPatternPool(sw->signal.__width); + pool = BitPatternPool(sw->signal.size()); } for (auto pat : cs2->compare) if (!pat.is_fully_const()) @@ -258,7 +258,7 @@ static void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc) { RTLIL::SigSpec sig = find_any_lvalue(&proc->root_case); - if (sig.__width == 0) + if (sig.size() == 0) break; if (first) { @@ -270,7 +270,7 @@ static void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc) log(" creating decoder for signal `%s'.\n", log_signal(sig)); - RTLIL::SigSpec value = signal_to_mux_tree(mod, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.__width)); + RTLIL::SigSpec value = signal_to_mux_tree(mod, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.size())); mod->connections.push_back(RTLIL::SigSig(sig, value)); } } |