aboutsummaryrefslogtreecommitdiffstats
path: root/passes/pmgen/peepopt_dffmux.pmg
diff options
context:
space:
mode:
Diffstat (limited to 'passes/pmgen/peepopt_dffmux.pmg')
-rw-r--r--passes/pmgen/peepopt_dffmux.pmg158
1 files changed, 108 insertions, 50 deletions
diff --git a/passes/pmgen/peepopt_dffmux.pmg b/passes/pmgen/peepopt_dffmux.pmg
index c88a52226..0069b0570 100644
--- a/passes/pmgen/peepopt_dffmux.pmg
+++ b/passes/pmgen/peepopt_dffmux.pmg
@@ -8,21 +8,23 @@ match dff
select GetSize(port(dff, \D)) > 1
endmatch
+code sigD
+ sigD = port(dff, \D);
+endcode
+
match rstmux
select rstmux->type == $mux
select GetSize(port(rstmux, \Y)) > 1
- index <SigSpec> port(rstmux, \Y) === port(dff, \D)
+ index <SigSpec> port(rstmux, \Y) === sigD
choice <IdString> BA {\B, \A}
select port(rstmux, BA).is_fully_const()
set rstmuxBA BA
- optional
+ semioptional
endmatch
code sigD
if (rstmux)
sigD = port(rstmux, rstmuxBA == \B ? \A : \B);
- else
- sigD = port(dff, \D);
endcode
match cemux
@@ -32,67 +34,111 @@ match cemux
choice <IdString> AB {\A, \B}
index <SigSpec> port(cemux, AB) === port(dff, \Q)
set cemuxAB AB
+ semioptional
endmatch
code
- SigSpec D = port(cemux, cemuxAB == \A ? \B : \A);
- SigSpec Q = port(dff, \Q);
+ if (!cemux && !rstmux)
+ reject;
+endcode
+
+code
Const rst;
- if (rstmux)
+ SigSpec D;
+ if (cemux) {
+ D = port(cemux, cemuxAB == \A ? \B : \A);
+ if (rstmux)
+ rst = port(rstmux, rstmuxBA).as_const();
+ else
+ rst = Const(State::Sx, GetSize(D));
+ }
+ else {
+ log_assert(rstmux);
+ D = port(rstmux, rstmuxBA == \B ? \A : \B);
rst = port(rstmux, rstmuxBA).as_const();
+ }
+ SigSpec Q = port(dff, \Q);
int width = GetSize(D);
- SigSpec &ceA = cemux->connections_.at(\A);
- SigSpec &ceB = cemux->connections_.at(\B);
- SigSpec &ceY = cemux->connections_.at(\Y);
- SigSpec &dffD = dff->connections_.at(\D);
- SigSpec &dffQ = dff->connections_.at(\Q);
+ SigSpec dffD = dff->getPort(\D);
+ SigSpec dffQ = dff->getPort(\Q);
- if (D[width-1] == D[width-2]) {
- did_something = true;
+ Const initval;
+ for (auto b : Q) {
+ auto it = initbits.find(b);
+ initval.bits.push_back(it == initbits.end() ? State::Sx : it->second);
+ }
- SigBit sign = D[width-1];
- bool is_signed = sign.wire;
- int i;
- for (i = width-1; i >= 2; i--) {
- if (!is_signed) {
- module->connect(Q[i], sign);
- if (D[i-1] != sign || (rst.size() && rst[i-1] != rst[width-1]))
- break;
- }
- else {
- module->connect(Q[i], Q[i-1]);
- if (D[i-2] != sign || (rst.size() && rst[i-1] != rst[width-1]))
- break;
- }
- }
+ auto cmpx = [=](State lhs, State rhs) {
+ if (lhs == State::Sx || rhs == State::Sx)
+ return true;
+ return lhs == rhs;
+ };
- ceA.remove(i, width-i);
- ceB.remove(i, width-i);
- ceY.remove(i, width-i);
- cemux->fixup_parameters();
- dffD.remove(i, width-i);
- dffQ.remove(i, width-i);
+ int i = width-1;
+ while (i > 1) {
+ if (D[i] != D[i-1])
+ break;
+ if (!cmpx(rst[i], rst[i-1]))
+ break;
+ if (!cmpx(initval[i], initval[i-1]))
+ break;
+ if (!cmpx(rst[i], initval[i]))
+ break;
+ rminitbits.insert(Q[i]);
+ module->connect(Q[i], Q[i-1]);
+ i--;
+ }
+ if (i < width-1) {
+ did_something = true;
+ if (cemux) {
+ SigSpec ceA = cemux->getPort(\A);
+ SigSpec ceB = cemux->getPort(\B);
+ SigSpec ceY = cemux->getPort(\Y);
+ ceA.remove(i, width-1-i);
+ ceB.remove(i, width-1-i);
+ ceY.remove(i, width-1-i);
+ cemux->setPort(\A, ceA);
+ cemux->setPort(\B, ceB);
+ cemux->setPort(\Y, ceY);
+ cemux->fixup_parameters();
+ blacklist(cemux);
+ }
+ if (rstmux) {
+ SigSpec rstA = rstmux->getPort(\A);
+ SigSpec rstB = rstmux->getPort(\B);
+ SigSpec rstY = rstmux->getPort(\Y);
+ rstA.remove(i, width-1-i);
+ rstB.remove(i, width-1-i);
+ rstY.remove(i, width-1-i);
+ rstmux->setPort(\A, rstA);
+ rstmux->setPort(\B, rstB);
+ rstmux->setPort(\Y, rstY);
+ rstmux->fixup_parameters();
+ blacklist(rstmux);
+ }
+ dffD.remove(i, width-1-i);
+ dffQ.remove(i, width-1-i);
+ dff->setPort(\D, dffD);
+ dff->setPort(\Q, dffQ);
dff->fixup_parameters();
+ blacklist(dff);
- log("dffcemux pattern in %s: dff=%s, cemux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux), width-i);
- accept;
+ log("dffcemux pattern in %s: dff=%s, cemux=%s, rstmux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux, "n/a"), log_id(rstmux, "n/a"), width-1-i);
+ width = i+1;
}
- else {
+ if (cemux) {
+ SigSpec ceA = cemux->getPort(\A);
+ SigSpec ceB = cemux->getPort(\B);
+ SigSpec ceY = cemux->getPort(\Y);
+
int count = 0;
for (int i = width-1; i >= 0; i--) {
if (D[i].wire)
continue;
- Wire *w = Q[i].wire;
- auto it = w->attributes.find(\init);
- State init;
- if (it != w->attributes.end())
- init = it->second[Q[i].offset];
- else
- init = State::Sx;
-
- if (init == State::Sx || init == D[i].data) {
+ if (cmpx(rst[i], D[i].data) && cmpx(initval[i], D[i].data)) {
count++;
+ rminitbits.insert(Q[i]);
module->connect(Q[i], D[i]);
ceA.remove(i);
ceB.remove(i);
@@ -101,13 +147,25 @@ code
dffQ.remove(i);
}
}
- if (count > 0) {
+ if (count > 0)
+ {
did_something = true;
+
+ cemux->setPort(\A, ceA);
+ cemux->setPort(\B, ceB);
+ cemux->setPort(\Y, ceY);
cemux->fixup_parameters();
+ blacklist(cemux);
+
+ dff->setPort(\D, dffD);
+ dff->setPort(\Q, dffQ);
dff->fixup_parameters();
- log("dffcemux pattern in %s: dff=%s, cemux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(cemux), count);
+ blacklist(dff);
+
+ log("dffcemux pattern in %s: dff=%s, cemux=%s, rstmux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(cemux), log_id(rstmux, "n/a"), count);
}
+ }
+ if (did_something)
accept;
- }
endcode
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-20 05:07:39 +0000