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-rw-r--r--passes/opt/opt_expr.cc4
-rw-r--r--passes/opt/opt_share.cc7
2 files changed, 8 insertions, 3 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 00d7d6063..6cf66fb95 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -953,6 +953,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
if (b.is_fully_const()) {
+ if (b.is_fully_undef()) {
+ RTLIL::SigSpec input = b;
+ ACTION_DO(ID::Y, Const(State::Sx, GetSize(cell->getPort(ID::Y))));
+ } else
if (b.as_bool() == (cell->type == ID($eq))) {
RTLIL::SigSpec input = b;
ACTION_DO(ID::Y, cell->getPort(ID::A));
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index c53fb3113..2c456705c 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -108,12 +108,13 @@ bool cell_supported(RTLIL::Cell *cell)
return false;
}
-std::map<IdString, IdString> mergeable_type_map{
- {ID($sub), ID($add)},
-};
+std::map<IdString, IdString> mergeable_type_map;
bool mergeable(RTLIL::Cell *a, RTLIL::Cell *b)
{
+ if (mergeable_type_map.empty()) {
+ mergeable_type_map.insert({ID($sub), ID($add)});
+ }
auto a_type = a->type;
if (mergeable_type_map.count(a_type))
a_type = mergeable_type_map.at(a_type);