diff options
Diffstat (limited to 'passes/opt')
-rw-r--r-- | passes/opt/opt_clean.cc | 8 | ||||
-rw-r--r-- | passes/opt/opt_expr.cc | 8 | ||||
-rw-r--r-- | passes/opt/opt_reduce.cc | 8 | ||||
-rw-r--r-- | passes/opt/pmux2shiftx.cc | 4 | ||||
-rw-r--r-- | passes/opt/share.cc | 16 | ||||
-rw-r--r-- | passes/opt/wreduce.cc | 2 |
6 files changed, 23 insertions, 23 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index cac265a52..07f9ee2a0 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -203,8 +203,8 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, SigPoo return !(w2->port_input && w2->port_output); if (w1->name[0] == '\\' && w2->name[0] == '\\') { - if (regs.check_any(s1) != regs.check_any(s2)) - return regs.check_any(s2); + if (regs.check(s1) != regs.check(s2)) + return regs.check(s2); if (direct_wires.count(w1) != direct_wires.count(w2)) return direct_wires.count(w2) != 0; if (conns.check_any(s1) != conns.check_any(s2)) @@ -358,8 +358,8 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos s2[i] = initval[i]; initval[i] = State::Sx; } - new_conn.first.append_bit(s1[i]); - new_conn.second.append_bit(s2[i]); + new_conn.first.append(s1[i]); + new_conn.second.append(s2[i]); } if (new_conn.first.size() > 0) { if (initval.is_fully_undef()) diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index a92643134..f9c5f68f2 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -192,11 +192,11 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ for (auto &it : grouped_bits[i]) { for (auto &bit : it.second) { - new_conn.first.append_bit(bit); - new_conn.second.append_bit(RTLIL::SigBit(new_y, new_a.size())); + new_conn.first.append(bit); + new_conn.second.append(RTLIL::SigBit(new_y, new_a.size())); } - new_a.append_bit(it.first.first); - new_b.append_bit(it.first.second); + new_a.append(it.first.first); + new_b.append(it.first.second); } if (cell->type.in(ID($and), ID($or)) && i == GRP_CONST_A) { diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index f74655d1c..fd734c387 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -192,13 +192,13 @@ struct OptReduceWorker if (all_tuple_bits_same) { - old_sig_conn.first.append_bit(sig_y.at(i)); - old_sig_conn.second.append_bit(sig_a.at(i)); + old_sig_conn.first.append(sig_y.at(i)); + old_sig_conn.second.append(sig_a.at(i)); } else if (consolidated_in_tuples_map.count(in_tuple)) { - old_sig_conn.first.append_bit(sig_y.at(i)); - old_sig_conn.second.append_bit(consolidated_in_tuples_map.at(in_tuple)); + old_sig_conn.first.append(sig_y.at(i)); + old_sig_conn.second.append(consolidated_in_tuples_map.at(in_tuple)); } else { diff --git a/passes/opt/pmux2shiftx.cc b/passes/opt/pmux2shiftx.cc index 92b5794ac..a7fefc291 100644 --- a/passes/opt/pmux2shiftx.cc +++ b/passes/opt/pmux2shiftx.cc @@ -331,7 +331,7 @@ struct Pmux2ShiftxPass : public Pass { pair<SigSpec, Const> entry; for (auto it : bits) { - entry.first.append_bit(it.first); + entry.first.append(it.first); entry.second.bits.push_back(it.second); } @@ -352,7 +352,7 @@ struct Pmux2ShiftxPass : public Pass { pair<SigSpec, Const> entry; for (auto it : bits) { - entry.first.append_bit(it.first); + entry.first.append(it.first); entry.second.bits.push_back(it.second); } diff --git a/passes/opt/share.cc b/passes/opt/share.cc index ec2e110a8..c11381138 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -516,7 +516,7 @@ struct ShareWorker if (unsigned_cell->getPort(ID::A).to_sigbit_vector().back() != RTLIL::State::S0) { unsigned_cell->parameters.at(ID(A_WIDTH)) = unsigned_cell->parameters.at(ID(A_WIDTH)).as_int() + 1; RTLIL::SigSpec new_a = unsigned_cell->getPort(ID::A); - new_a.append_bit(RTLIL::State::S0); + new_a.append(RTLIL::State::S0); unsigned_cell->setPort(ID::A, new_a); } unsigned_cell->parameters.at(ID(A_SIGNED)) = true; @@ -588,7 +588,7 @@ struct ShareWorker if (unsigned_cell->getPort(ID::A).to_sigbit_vector().back() != RTLIL::State::S0) { unsigned_cell->parameters.at(ID(A_WIDTH)) = unsigned_cell->parameters.at(ID(A_WIDTH)).as_int() + 1; RTLIL::SigSpec new_a = unsigned_cell->getPort(ID::A); - new_a.append_bit(RTLIL::State::S0); + new_a.append(RTLIL::State::S0); unsigned_cell->setPort(ID::A, new_a); } unsigned_cell->parameters.at(ID(A_SIGNED)) = true; @@ -601,7 +601,7 @@ struct ShareWorker if (unsigned_cell->getPort(ID::B).to_sigbit_vector().back() != RTLIL::State::S0) { unsigned_cell->parameters.at(ID(B_WIDTH)) = unsigned_cell->parameters.at(ID(B_WIDTH)).as_int() + 1; RTLIL::SigSpec new_b = unsigned_cell->getPort(ID::B); - new_b.append_bit(RTLIL::State::S0); + new_b.append(RTLIL::State::S0); unsigned_cell->setPort(ID::B, new_b); } unsigned_cell->parameters.at(ID(B_SIGNED)) = true; @@ -790,7 +790,7 @@ struct ShareWorker p.second.bits.clear(); for (auto &it : p_bits) { - p.first.append_bit(it.first); + p.first.append(it.first); p.second.bits.push_back(it.second); } @@ -906,14 +906,14 @@ struct ShareWorker if (used_in_a) for (auto p : c_patterns) { for (int i = 0; i < GetSize(sig_s); i++) - p.first.append_bit(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0); + p.first.append(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0); if (sort_check_activation_pattern(p)) activation_patterns_cache[cell].insert(p); } for (int idx : used_in_b_parts) for (auto p : c_patterns) { - p.first.append_bit(sig_s[idx]), p.second.bits.push_back(RTLIL::State::S1); + p.first.append(sig_s[idx]), p.second.bits.push_back(RTLIL::State::S1); if (sort_check_activation_pattern(p)) activation_patterns_cache[cell].insert(p); } @@ -948,7 +948,7 @@ struct ShareWorker RTLIL::SigSpec signal; for (auto &bit : all_bits) - signal.append_bit(bit); + signal.append(bit); return signal; } @@ -963,7 +963,7 @@ struct ShareWorker for (int i = 0; i < GetSize(p_first); i++) if (filter_bits.count(p_first[i]) == 0) { - new_p.first.append_bit(p_first[i]); + new_p.first.append(p_first[i]); new_p.second.bits.push_back(p.second.bits.at(i)); } diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 04b882db9..b5451849d 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -98,7 +98,7 @@ struct WreduceWorker SigSpec sig_removed; for (int i = GetSize(bits_removed)-1; i >= 0; i--) - sig_removed.append_bit(bits_removed[i]); + sig_removed.append(bits_removed[i]); if (GetSize(bits_removed) == GetSize(sig_y)) { log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); |