diff options
Diffstat (limited to 'passes/memory')
| -rw-r--r-- | passes/memory/Makefile.inc | 1 | ||||
| -rw-r--r-- | passes/memory/memory.cc | 6 | ||||
| -rw-r--r-- | passes/memory/memory_collect.cc | 102 | ||||
| -rw-r--r-- | passes/memory/memory_dff.cc | 125 | ||||
| -rw-r--r-- | passes/memory/memory_map.cc | 513 | ||||
| -rw-r--r-- | passes/memory/memory_share.cc | 744 | ||||
| -rw-r--r-- | passes/memory/memory_unpack.cc | 40 |
7 files changed, 1119 insertions, 412 deletions
diff --git a/passes/memory/Makefile.inc b/passes/memory/Makefile.inc index 21f17db5b..026c5ff85 100644 --- a/passes/memory/Makefile.inc +++ b/passes/memory/Makefile.inc @@ -1,6 +1,7 @@ OBJS += passes/memory/memory.o OBJS += passes/memory/memory_dff.o +OBJS += passes/memory/memory_share.o OBJS += passes/memory/memory_collect.o OBJS += passes/memory/memory_unpack.o OBJS += passes/memory/memory_map.o diff --git a/passes/memory/memory.cc b/passes/memory/memory.cc index 680657a79..fc3095535 100644 --- a/passes/memory/memory.cc +++ b/passes/memory/memory.cc @@ -33,6 +33,9 @@ struct MemoryPass : public Pass { log("This pass calls all the other memory_* passes in a useful order:\n"); log("\n"); log(" memory_dff\n"); + log(" opt_clean\n"); + log(" memory_share\n"); + log(" opt_clean\n"); log(" memory_collect\n"); log(" memory_map (skipped if called with -nomap)\n"); log("\n"); @@ -58,6 +61,9 @@ struct MemoryPass : public Pass { extra_args(args, argidx, design); Pass::call(design, "memory_dff"); + Pass::call(design, "opt_clean"); + Pass::call(design, "memory_share"); + Pass::call(design, "opt_clean"); Pass::call(design, "memory_collect"); if (!flag_nomap) diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 6fe5e162c..9c670f00f 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -22,7 +22,6 @@ #include <sstream> #include <algorithm> #include <stdlib.h> -#include <assert.h> static bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b) { @@ -58,12 +57,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) RTLIL::SigSpec sig_rd_addr; RTLIL::SigSpec sig_rd_data; - std::vector<std::string> del_cell_ids; + std::vector<RTLIL::Cell*> del_cells; std::vector<RTLIL::Cell*> memcells; - for (auto &cell_it : module->cells) { + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; - if ((cell->type == "$memwr" || cell->type == "$memrd") && cell->parameters["\\MEMID"].decode_string() == memory->name) + if ((cell->type == "$memwr" || cell->type == "$memrd") && memory->name == cell->parameters["\\MEMID"].decode_string()) memcells.push_back(cell); } @@ -71,24 +70,24 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) for (auto cell : memcells) { - if (cell->type == "$memwr" && cell->parameters["\\MEMID"].decode_string() == memory->name) + if (cell->type == "$memwr" && memory->name == cell->parameters["\\MEMID"].decode_string()) { wr_ports++; - del_cell_ids.push_back(cell->name); + del_cells.push_back(cell); - RTLIL::SigSpec clk = cell->connections["\\CLK"]; + RTLIL::SigSpec clk = cell->getPort("\\CLK"); RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]); RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]); - RTLIL::SigSpec addr = cell->connections["\\ADDR"]; - RTLIL::SigSpec data = cell->connections["\\DATA"]; - RTLIL::SigSpec en = cell->connections["\\EN"]; + RTLIL::SigSpec addr = cell->getPort("\\ADDR"); + RTLIL::SigSpec data = cell->getPort("\\DATA"); + RTLIL::SigSpec en = cell->getPort("\\EN"); clk.extend(1, false); clk_enable.extend(1, false); clk_polarity.extend(1, false); addr.extend(addr_bits, false); data.extend(memory->width, false); - en.extend(1, false); + en.extend(memory->width, false); sig_wr_clk.append(clk); sig_wr_clk_enable.append(clk_enable); @@ -98,17 +97,17 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) sig_wr_en.append(en); } - if (cell->type == "$memrd" && cell->parameters["\\MEMID"].decode_string() == memory->name) + if (cell->type == "$memrd" && memory->name == cell->parameters["\\MEMID"].decode_string()) { rd_ports++; - del_cell_ids.push_back(cell->name); + del_cells.push_back(cell); - RTLIL::SigSpec clk = cell->connections["\\CLK"]; + RTLIL::SigSpec clk = cell->getPort("\\CLK"); RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]); RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]); RTLIL::SigSpec transparent = RTLIL::SigSpec(cell->parameters["\\TRANSPARENT"]); - RTLIL::SigSpec addr = cell->connections["\\ADDR"]; - RTLIL::SigSpec data = cell->connections["\\DATA"]; + RTLIL::SigSpec addr = cell->getPort("\\ADDR"); + RTLIL::SigSpec data = cell->getPort("\\DATA"); clk.extend(1, false); clk_enable.extend(1, false); @@ -127,61 +126,48 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) } std::stringstream sstr; - sstr << "$mem$" << memory->name << "$" << (RTLIL::autoidx++); + sstr << "$mem$" << memory->name.str() << "$" << (autoidx++); - RTLIL::Cell *mem = new RTLIL::Cell; - mem->name = sstr.str(); - mem->type = "$mem"; - - mem->parameters["\\MEMID"] = RTLIL::Const(memory->name); + RTLIL::Cell *mem = module->addCell(sstr.str(), "$mem"); + mem->parameters["\\MEMID"] = RTLIL::Const(memory->name.str()); mem->parameters["\\WIDTH"] = RTLIL::Const(memory->width); mem->parameters["\\OFFSET"] = RTLIL::Const(memory->start_offset); mem->parameters["\\SIZE"] = RTLIL::Const(memory->size); mem->parameters["\\ABITS"] = RTLIL::Const(addr_bits); - sig_wr_clk_enable.optimize(); - sig_wr_clk_polarity.optimize(); - - assert(sig_wr_clk.width == wr_ports); - assert(sig_wr_clk_enable.width == wr_ports && sig_wr_clk_enable.is_fully_const()); - assert(sig_wr_clk_polarity.width == wr_ports && sig_wr_clk_polarity.is_fully_const()); - assert(sig_wr_addr.width == wr_ports * addr_bits); - assert(sig_wr_data.width == wr_ports * memory->width); - assert(sig_wr_en.width == wr_ports); + log_assert(sig_wr_clk.size() == wr_ports); + log_assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const()); + log_assert(sig_wr_clk_polarity.size() == wr_ports && sig_wr_clk_polarity.is_fully_const()); + log_assert(sig_wr_addr.size() == wr_ports * addr_bits); + log_assert(sig_wr_data.size() == wr_ports * memory->width); + log_assert(sig_wr_en.size() == wr_ports * memory->width); mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports); - mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.chunks[0].data : RTLIL::Const(0, 0); - mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.chunks[0].data : RTLIL::Const(0, 0); + mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0); + mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : RTLIL::Const(0, 0); - mem->connections["\\WR_CLK"] = sig_wr_clk; - mem->connections["\\WR_ADDR"] = sig_wr_addr; - mem->connections["\\WR_DATA"] = sig_wr_data; - mem->connections["\\WR_EN"] = sig_wr_en; + mem->setPort("\\WR_CLK", sig_wr_clk); + mem->setPort("\\WR_ADDR", sig_wr_addr); + mem->setPort("\\WR_DATA", sig_wr_data); + mem->setPort("\\WR_EN", sig_wr_en); - sig_rd_clk_enable.optimize(); - sig_rd_clk_polarity.optimize(); - sig_rd_transparent.optimize(); - - assert(sig_rd_clk.width == rd_ports); - assert(sig_rd_clk_enable.width == rd_ports && sig_rd_clk_enable.is_fully_const()); - assert(sig_rd_clk_polarity.width == rd_ports && sig_rd_clk_polarity.is_fully_const()); - assert(sig_rd_addr.width == rd_ports * addr_bits); - assert(sig_rd_data.width == rd_ports * memory->width); + log_assert(sig_rd_clk.size() == rd_ports); + log_assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const()); + log_assert(sig_rd_clk_polarity.size() == rd_ports && sig_rd_clk_polarity.is_fully_const()); + log_assert(sig_rd_addr.size() == rd_ports * addr_bits); + log_assert(sig_rd_data.size() == rd_ports * memory->width); mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports); - mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.chunks[0].data : RTLIL::Const(0, 0); - mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.chunks[0].data : RTLIL::Const(0, 0); - mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.chunks[0].data : RTLIL::Const(0, 0); + mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : RTLIL::Const(0, 0); + mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : RTLIL::Const(0, 0); + mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : RTLIL::Const(0, 0); - mem->connections["\\RD_CLK"] = sig_rd_clk; - mem->connections["\\RD_ADDR"] = sig_rd_addr; - mem->connections["\\RD_DATA"] = sig_rd_data; + mem->setPort("\\RD_CLK", sig_rd_clk); + mem->setPort("\\RD_ADDR", sig_rd_addr); + mem->setPort("\\RD_DATA", sig_rd_data); - for (auto &id : del_cell_ids) { - delete module->cells[id]; - module->cells.erase(id); - } - module->cells[mem->name] = mem; + for (auto c : del_cells) + module->remove(c); } static void handle_module(RTLIL::Design *design, RTLIL::Module *module) @@ -213,7 +199,7 @@ struct MemoryCollectPass : public Pass { virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { log_header("Executing MEMORY_COLLECT pass (generating $mem cells).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) handle_module(design, mod_it.second); } diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 2502a8b61..302ab3abf 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -20,51 +20,41 @@ #include "kernel/register.h" #include "kernel/log.h" #include <stdlib.h> -#include <assert.h> #include <sstream> static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig) { - for (auto &conn : module->connections) + for (auto &conn : module->connections()) sig.replace(conn.first, conn.second); } -static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false) +static bool find_sig_before_dff(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false) { normalize_sig(module, sig); - sig.expand(); - for (size_t i = 0; i < sig.chunks.size(); i++) + for (auto &bit : sig) { - RTLIL::SigChunk &chunk = sig.chunks[i]; - - if (chunk.wire == NULL) + if (bit.wire == NULL) continue; - for (auto &cell_it : module->cells) + for (auto cell : dff_cells) { - RTLIL::Cell *cell = cell_it.second; - - if (cell->type != "$dff") - continue; - if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) { - if (cell->connections["\\CLK"] != clk) + if (cell->getPort("\\CLK") != clk) continue; if (cell->parameters["\\CLK_POLARITY"].as_bool() != clk_polarity) continue; } - RTLIL::SigSpec q_norm = cell->connections[after ? "\\D" : "\\Q"]; + RTLIL::SigSpec q_norm = cell->getPort(after ? "\\D" : "\\Q"); normalize_sig(module, q_norm); - RTLIL::SigSpec d = q_norm.extract(chunk, &cell->connections[after ? "\\Q" : "\\D"]); - if (d.width != 1) + RTLIL::SigSpec d = q_norm.extract(bit, &cell->getPort(after ? "\\Q" : "\\D")); + if (d.size() != 1) continue; - assert(d.chunks.size() == 1); - chunk = d.chunks[0]; - clk = cell->connections["\\CLK"]; + bit = d; + clk = cell->getPort("\\CLK"); clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool(); goto replaced_this_bit; } @@ -73,44 +63,46 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI replaced_this_bit:; } - sig.optimize(); return true; } -static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell) +static void handle_wr_cell(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::Cell *cell) { log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str()); RTLIL::SigSpec clk = RTLIL::SigSpec(RTLIL::State::Sx); bool clk_polarity = 0; - RTLIL::SigSpec sig_addr = cell->connections["\\ADDR"]; - if (!find_sig_before_dff(module, sig_addr, clk, clk_polarity)) { + RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR"); + if (!find_sig_before_dff(module, dff_cells, sig_addr, clk, clk_polarity)) { log("no (compatible) $dff for address input found.\n"); return; } - RTLIL::SigSpec sig_data = cell->connections["\\DATA"]; - if (!find_sig_before_dff(module, sig_data, clk, clk_polarity)) { + RTLIL::SigSpec sig_data = cell->getPort("\\DATA"); + if (!find_sig_before_dff(module, dff_cells, sig_data, clk, clk_polarity)) { log("no (compatible) $dff for data input found.\n"); return; } - RTLIL::SigSpec sig_en = cell->connections["\\EN"]; - if (!find_sig_before_dff(module, sig_en, clk, clk_polarity)) { + RTLIL::SigSpec sig_en = cell->getPort("\\EN"); + if (!find_sig_before_dff(module, dff_cells, sig_en, clk, clk_polarity)) { log("no (compatible) $dff for enable input found.\n"); return; } if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) { - cell->connections["\\CLK"] = clk; - cell->connections["\\ADDR"] = sig_addr; - cell->connections["\\DATA"] = sig_data; - cell->connections["\\EN"] = sig_en; + cell->setPort("\\CLK", clk); + cell->setPort("\\ADDR", sig_addr); + cell->setPort("\\DATA", sig_data); + cell->setPort("\\EN", sig_en); cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); log("merged $dff to cell.\n"); + return; } + + log("no (compatible) $dff found.\n"); } static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig) @@ -119,36 +111,32 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig) sig.sort_and_unify(); std::stringstream sstr; - sstr << "$memory_dff_disconnected$" << (RTLIL::autoidx++); + sstr << "$memory_dff_disconnected$" << (autoidx++); - RTLIL::Wire *wire = new RTLIL::Wire; - wire->name = sstr.str(); - wire->width = sig.width; - module->wires[wire->name] = wire; + RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size()); - RTLIL::SigSpec newsig(wire); - - for (auto &cell_it : module->cells) { - RTLIL::Cell *cell = cell_it.second; - if (cell->type == "$dff") - cell->connections["\\Q"].replace(sig, newsig); - } + for (auto cell : module->cells()) + if (cell->type == "$dff") { + RTLIL::SigSpec new_q = cell->getPort("\\Q"); + new_q.replace(sig, new_sig); + cell->setPort("\\Q", new_q); + } } -static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell) +static void handle_rd_cell(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::Cell *cell) { log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str()); bool clk_polarity = 0; RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx); - RTLIL::SigSpec sig_data = cell->connections["\\DATA"]; - if (find_sig_before_dff(module, sig_data, clk_data, clk_polarity, true) && + RTLIL::SigSpec sig_data = cell->getPort("\\DATA"); + if (find_sig_before_dff(module, dff_cells, sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx)) { disconnect_dff(module, sig_data); - cell->connections["\\CLK"] = clk_data; - cell->connections["\\DATA"] = sig_data; + cell->setPort("\\CLK", clk_data); + cell->setPort("\\DATA", sig_data); cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0); @@ -157,12 +145,12 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell) } RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx); - RTLIL::SigSpec sig_addr = cell->connections["\\ADDR"]; - if (find_sig_before_dff(module, sig_addr, clk_addr, clk_polarity) && + RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR"); + if (find_sig_before_dff(module, dff_cells, sig_addr, clk_addr, clk_polarity) && clk_addr != RTLIL::SigSpec(RTLIL::State::Sx)) { - cell->connections["\\CLK"] = clk_addr; - cell->connections["\\ADDR"] = sig_addr; + cell->setPort("\\CLK", clk_addr); + cell->setPort("\\ADDR", sig_addr); cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1); @@ -173,16 +161,22 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell) log("no (compatible) $dff found.\n"); } -static void handle_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_wr_only) +static void handle_module(RTLIL::Module *module, bool flag_wr_only) { - for (auto &cell_it : module->cells) { - if (!design->selected(module, cell_it.second)) - continue; - if (cell_it.second->type == "$memwr" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool()) - handle_wr_cell(module, cell_it.second); - if (!flag_wr_only && cell_it.second->type == "$memrd" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool()) - handle_rd_cell(module, cell_it.second); - } + std::vector<RTLIL::Cell*> dff_cells; + + for (auto cell : module->cells()) + if (cell->type == "$dff") + dff_cells.push_back(cell); + + for (auto cell : module->selected_cells()) + if (cell->type == "$memwr" && !cell->parameters["\\CLK_ENABLE"].as_bool()) + handle_wr_cell(module, dff_cells, cell); + + if (!flag_wr_only) + for (auto cell : module->selected_cells()) + if (cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool()) + handle_rd_cell(module, dff_cells, cell); } struct MemoryDffPass : public Pass { @@ -217,9 +211,8 @@ struct MemoryDffPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod_it : design->modules) - if (design->selected(mod_it.second)) - handle_module(design, mod_it.second, flag_wr_only); + for (auto mod : design->selected_modules()) + handle_module(mod, flag_wr_only); } } MemoryDffPass; diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index e0e3802d1..eecb6f35d 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -22,316 +22,302 @@ #include <sstream> #include <set> #include <stdlib.h> -#include <assert.h> -static std::string genid(std::string name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "") +struct MemoryMapWorker { - std::stringstream sstr; - sstr << "$memory" << name << token1; - - if (i >= 0) - sstr << "[" << i << "]"; + RTLIL::Design *design; + RTLIL::Module *module; - sstr << token2; + std::map<std::pair<RTLIL::SigSpec, RTLIL::SigSpec>, RTLIL::SigBit> decoder_cache; - if (j >= 0) - sstr << "[" << j << "]"; + std::string genid(RTLIL::IdString name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "") + { + std::stringstream sstr; + sstr << "$memory" << name.str() << token1; + + if (i >= 0) + sstr << "[" << i << "]"; - sstr << token3; + sstr << token2; - if (k >= 0) - sstr << "[" << k << "]"; + if (j >= 0) + sstr << "[" << j << "]"; - sstr << token4 << "$" << (RTLIL::autoidx++); - return sstr.str(); -} + sstr << token3; -static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) -{ - std::set<int> static_ports; - std::map<int, RTLIL::SigSpec> static_cells_map; - int mem_size = cell->parameters["\\SIZE"].as_int(); - int mem_width = cell->parameters["\\WIDTH"].as_int(); - int mem_offset = cell->parameters["\\OFFSET"].as_int(); - int mem_abits = cell->parameters["\\ABITS"].as_int(); - - // delete unused memory cell - if (cell->parameters["\\RD_PORTS"].as_int() == 0 && cell->parameters["\\WR_PORTS"].as_int() == 0) { - module->cells.erase(cell->name); - delete cell; - return; - } + if (k >= 0) + sstr << "[" << k << "]"; - // all write ports must share the same clock - RTLIL::SigSpec clocks = cell->connections["\\WR_CLK"]; - RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"]; - RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; - RTLIL::SigSpec refclock; - RTLIL::State refclock_pol = RTLIL::State::Sx; - for (int i = 0; i < clocks.width; i++) { - RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(i, 1); - if (wr_en.is_fully_const() && wr_en.as_int() == 0) { - static_ports.insert(i); - continue; - } - if (clocks_en.bits[i] != RTLIL::State::S1) { - RTLIL::SigSpec wr_addr = cell->connections["\\WR_ADDR"].extract(i*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->connections["\\WR_DATA"].extract(i*mem_width, mem_width); - if (wr_addr.is_fully_const()) { - // FIXME: Actually we should check for wr_en.is_fully_const() also and - // create a $adff cell with this ports wr_en input as reset pin when wr_en - // is not a simple static 1. - static_cells_map[wr_addr.as_int()] = wr_data; - static_ports.insert(i); - continue; - } - log("Not mapping memory cell %s in module %s (write port %d has no clock).\n", - cell->name.c_str(), module->name.c_str(), i); - return; - } - if (refclock.width == 0) { - refclock = clocks.extract(i, 1); - refclock_pol = clocks_pol.bits[i]; - } - if (clocks.extract(i, 1) != refclock || clocks_pol.bits[i] != refclock_pol) { - log("Not mapping memory cell %s in module %s (write clock %d is incompatible with other clocks).\n", - cell->name.c_str(), module->name.c_str(), i); - return; - } + sstr << token4 << "$" << (autoidx++); + return sstr.str(); } - log("Mapping memory cell %s in module %s:\n", cell->name.c_str(), module->name.c_str()); + RTLIL::Wire *addr_decode(RTLIL::SigSpec addr_sig, RTLIL::SigSpec addr_val) + { + std::pair<RTLIL::SigSpec, RTLIL::SigSpec> key(addr_sig, addr_val); + log_assert(SIZE(addr_sig) == SIZE(addr_val)); - std::vector<RTLIL::SigSpec> data_reg_in; - std::vector<RTLIL::SigSpec> data_reg_out; + if (decoder_cache.count(key) == 0) { + if (SIZE(addr_sig) < 2) { + decoder_cache[key] = module->Eq(NEW_ID, addr_sig, addr_val); + } else { + int split_at = SIZE(addr_sig) / 2; + RTLIL::SigBit left_eq = addr_decode(addr_sig.extract(0, split_at), addr_val.extract(0, split_at)); + RTLIL::SigBit right_eq = addr_decode(addr_sig.extract(split_at, SIZE(addr_sig) - split_at), addr_val.extract(split_at, SIZE(addr_val) - split_at)); + decoder_cache[key] = module->And(NEW_ID, left_eq, right_eq); + } + } - int count_static = 0; + RTLIL::SigBit bit = decoder_cache.at(key); + log_assert(bit.wire != nullptr && SIZE(bit.wire) == 1); + return bit.wire; + } - for (int i = 0; i < mem_size; i++) + void handle_cell(RTLIL::Cell *cell) { - if (static_cells_map.count(i) > 0) - { - data_reg_in.push_back(RTLIL::SigSpec(RTLIL::State::Sz, mem_width)); - data_reg_out.push_back(static_cells_map[i]); - count_static++; + std::set<int> static_ports; + std::map<int, RTLIL::SigSpec> static_cells_map; + int mem_size = cell->parameters["\\SIZE"].as_int(); + int mem_width = cell->parameters["\\WIDTH"].as_int(); + int mem_offset = cell->parameters["\\OFFSET"].as_int(); + int mem_abits = cell->parameters["\\ABITS"].as_int(); + + // delete unused memory cell + if (cell->parameters["\\RD_PORTS"].as_int() == 0 && cell->parameters["\\WR_PORTS"].as_int() == 0) { + module->remove(cell); + return; } - else - { - RTLIL::Cell *c = new RTLIL::Cell; - c->name = genid(cell->name, "", i); - c->type = "$dff"; - c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - if (clocks_pol.bits.size() > 0) { - c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]); - c->connections["\\CLK"] = clocks.extract(0, 1); - } else { - c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1); - c->connections["\\CLK"] = RTLIL::SigSpec(RTLIL::State::S0); + + // all write ports must share the same clock + RTLIL::SigSpec clocks = cell->getPort("\\WR_CLK"); + RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"]; + RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; + RTLIL::SigSpec refclock; + RTLIL::State refclock_pol = RTLIL::State::Sx; + for (int i = 0; i < clocks.size(); i++) { + RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(i * mem_width, mem_width); + if (wr_en.is_fully_const() && !wr_en.as_bool()) { + static_ports.insert(i); + continue; + } + if (clocks_en.bits[i] != RTLIL::State::S1) { + RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(i*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(i*mem_width, mem_width); + if (wr_addr.is_fully_const()) { + // FIXME: Actually we should check for wr_en.is_fully_const() also and + // create a $adff cell with this ports wr_en input as reset pin when wr_en + // is not a simple static 1. + static_cells_map[wr_addr.as_int()] = wr_data; + static_ports.insert(i); + continue; + } + log("Not mapping memory cell %s in module %s (write port %d has no clock).\n", + cell->name.c_str(), module->name.c_str(), i); + return; + } + if (refclock.size() == 0) { + refclock = clocks.extract(i, 1); + refclock_pol = clocks_pol.bits[i]; + } + if (clocks.extract(i, 1) != refclock || clocks_pol.bits[i] != refclock_pol) { + log("Not mapping memory cell %s in module %s (write clock %d is incompatible with other clocks).\n", + cell->name.c_str(), module->name.c_str(), i); + return; } - module->cells[c->name] = c; - - RTLIL::Wire *w_in = new RTLIL::Wire; - w_in->name = genid(cell->name, "", i, "$d"); - w_in->width = mem_width; - module->wires[w_in->name] = w_in; - data_reg_in.push_back(RTLIL::SigSpec(w_in)); - c->connections["\\D"] = data_reg_in.back(); - - RTLIL::Wire *w_out = new RTLIL::Wire; - w_out->name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); - if (module->wires.count(w_out->name) > 0) - w_out->name = genid(cell->name, "", i, "$q"); - w_out->width = mem_width; - w_out->start_offset = mem_offset; - module->wires[w_out->name] = w_out; - data_reg_out.push_back(RTLIL::SigSpec(w_out)); - c->connections["\\Q"] = data_reg_out.back(); } - } - log(" created %d $dff cells and %d static cells of width %d.\n", mem_size-count_static, count_static, mem_width); + log("Mapping memory cell %s in module %s:\n", cell->name.c_str(), module->name.c_str()); - int count_dff = 0, count_mux = 0, count_wrmux = 0; - - for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++) - { - RTLIL::SigSpec rd_addr = cell->connections["\\RD_ADDR"].extract(i*mem_abits, mem_abits); + std::vector<RTLIL::SigSpec> data_reg_in; + std::vector<RTLIL::SigSpec> data_reg_out; - std::vector<RTLIL::SigSpec> rd_signals; - rd_signals.push_back(cell->connections["\\RD_DATA"].extract(i*mem_width, mem_width)); + int count_static = 0; - if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1) + for (int i = 0; i < mem_size; i++) { - if (cell->parameters["\\RD_TRANSPARENT"].bits[i] == RTLIL::State::S1) + if (static_cells_map.count(i) > 0) { - RTLIL::Cell *c = new RTLIL::Cell; - c->name = genid(cell->name, "$rdreg", i); - c->type = "$dff"; - c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits); - c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - c->connections["\\CLK"] = cell->connections["\\RD_CLK"].extract(i, 1); - c->connections["\\D"] = rd_addr; - module->cells[c->name] = c; - count_dff++; - - RTLIL::Wire *w = new RTLIL::Wire; - w->name = genid(cell->name, "$rdreg", i, "$q"); - w->width = mem_abits; - module->wires[w->name] = w; - - c->connections["\\Q"] = RTLIL::SigSpec(w); - rd_addr = RTLIL::SigSpec(w); + data_reg_in.push_back(RTLIL::SigSpec(RTLIL::State::Sz, mem_width)); + data_reg_out.push_back(static_cells_map[i]); + count_static++; } else { - RTLIL::Cell *c = new RTLIL::Cell; - c->name = genid(cell->name, "$rdreg", i); - c->type = "$dff"; + RTLIL::Cell *c = module->addCell(genid(cell->name, "", i), "$dff"); c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - c->connections["\\CLK"] = cell->connections["\\RD_CLK"].extract(i, 1); - c->connections["\\Q"] = rd_signals.back(); - module->cells[c->name] = c; - count_dff++; - - RTLIL::Wire *w = new RTLIL::Wire; - w->name = genid(cell->name, "$rdreg", i, "$d"); - w->width = mem_width; - module->wires[w->name] = w; - - rd_signals.clear(); - rd_signals.push_back(RTLIL::SigSpec(w)); - c->connections["\\D"] = rd_signals.back(); + if (clocks_pol.bits.size() > 0) { + c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]); + c->setPort("\\CLK", clocks.extract(0, 1)); + } else { + c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1); + c->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::S0)); + } + + RTLIL::Wire *w_in = module->addWire(genid(cell->name, "", i, "$d"), mem_width); + data_reg_in.push_back(RTLIL::SigSpec(w_in)); + c->setPort("\\D", data_reg_in.back()); + + std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); + if (module->wires_.count(w_out_name) > 0) + w_out_name = genid(cell->name, "", i, "$q"); + + RTLIL::Wire *w_out = module->addWire(w_out_name, mem_width); + w_out->start_offset = mem_offset; + + data_reg_out.push_back(RTLIL::SigSpec(w_out)); + c->setPort("\\Q", data_reg_out.back()); } } - for (int j = 0; j < mem_abits; j++) + log(" created %d $dff cells and %d static cells of width %d.\n", mem_size-count_static, count_static, mem_width); + + int count_dff = 0, count_mux = 0, count_wrmux = 0; + + for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++) { - std::vector<RTLIL::SigSpec> next_rd_signals; + RTLIL::SigSpec rd_addr = cell->getPort("\\RD_ADDR").extract(i*mem_abits, mem_abits); + + std::vector<RTLIL::SigSpec> rd_signals; + rd_signals.push_back(cell->getPort("\\RD_DATA").extract(i*mem_width, mem_width)); - for (size_t k = 0; k < rd_signals.size(); k++) + if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1) { - RTLIL::Cell *c = new RTLIL::Cell; - c->name = genid(cell->name, "$rdmux", i, "", j, "", k); - c->type = "$mux"; - c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - c->connections["\\Y"] = rd_signals[k]; - c->connections["\\S"] = rd_addr.extract(mem_abits-j-1, 1); - module->cells[c->name] = c; - count_mux++; - - RTLIL::Wire *w = new RTLIL::Wire; - w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$a"); - w->width = mem_width; - module->wires[w->name] = w; - c->connections["\\A"] = RTLIL::SigSpec(w); - - w = new RTLIL::Wire; - w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$b"); - w->width = mem_width; - module->wires[w->name] = w; - c->connections["\\B"] = RTLIL::SigSpec(w); - - next_rd_signals.push_back(c->connections["\\A"]); - next_rd_signals.push_back(c->connections["\\B"]); + if (cell->parameters["\\RD_TRANSPARENT"].bits[i] == RTLIL::State::S1) + { + RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); + c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits); + c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); + c->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1)); + c->setPort("\\D", rd_addr); + count_dff++; + + RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$q"), mem_abits); + + c->setPort("\\Q", RTLIL::SigSpec(w)); + rd_addr = RTLIL::SigSpec(w); + } + else + { + RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); + c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; + c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); + c->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1)); + c->setPort("\\Q", rd_signals.back()); + count_dff++; + + RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$d"), mem_width); + + rd_signals.clear(); + rd_signals.push_back(RTLIL::SigSpec(w)); + c->setPort("\\D", rd_signals.back()); + } } - next_rd_signals.swap(rd_signals); - } + for (int j = 0; j < mem_abits; j++) + { + std::vector<RTLIL::SigSpec> next_rd_signals; - for (int j = 0; j < mem_size; j++) - module->connections.push_back(RTLIL::SigSig(rd_signals[j], data_reg_out[j])); - } + for (size_t k = 0; k < rd_signals.size(); k++) + { + RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux"); + c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; + c->setPort("\\Y", rd_signals[k]); + c->setPort("\\S", rd_addr.extract(mem_abits-j-1, 1)); + count_mux++; - log(" read interface: %d $dff and %d $mux cells.\n", count_dff, count_mux); + c->setPort("\\A", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width)); + c->setPort("\\B", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width)); - for (int i = 0; i < mem_size; i++) - { - if (static_cells_map.count(i) > 0) - continue; + next_rd_signals.push_back(c->getPort("\\A")); + next_rd_signals.push_back(c->getPort("\\B")); + } - RTLIL::SigSpec sig = data_reg_out[i]; + next_rd_signals.swap(rd_signals); + } - for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++) + for (int j = 0; j < mem_size; j++) + module->connect(RTLIL::SigSig(rd_signals[j], data_reg_out[j])); + } + + log(" read interface: %d $dff and %d $mux cells.\n", count_dff, count_mux); + + for (int i = 0; i < mem_size; i++) { - RTLIL::SigSpec wr_addr = cell->connections["\\WR_ADDR"].extract(j*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->connections["\\WR_DATA"].extract(j*mem_width, mem_width); - RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(j, 1); - - RTLIL::Cell *c = new RTLIL::Cell; - c->name = genid(cell->name, "$wreq", i, "", j); - c->type = "$eq"; - c->parameters["\\A_SIGNED"] = RTLIL::Const(0); - c->parameters["\\B_SIGNED"] = RTLIL::Const(0); - c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"]; - c->parameters["\\B_WIDTH"] = cell->parameters["\\ABITS"]; - c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->connections["\\A"] = RTLIL::SigSpec(i, mem_abits); - c->connections["\\B"] = wr_addr; - module->cells[c->name] = c; - count_wrmux++; - - RTLIL::Wire *w = new RTLIL::Wire; - w->name = genid(cell->name, "$wreq", i, "", j, "$y"); - module->wires[w->name] = w; - c->connections["\\Y"] = RTLIL::SigSpec(w); - - if (wr_en != RTLIL::SigSpec(1, 1)) + if (static_cells_map.count(i) > 0) + continue; + + RTLIL::SigSpec sig = data_reg_out[i]; + + for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++) { - c = new RTLIL::Cell; - c->name = genid(cell->name, "$wren", i, "", j); - c->type = "$and"; - c->parameters["\\A_SIGNED"] = RTLIL::Const(0); - c->parameters["\\B_SIGNED"] = RTLIL::Const(0); - c->parameters["\\A_WIDTH"] = RTLIL::Const(1); - c->parameters["\\B_WIDTH"] = RTLIL::Const(1); - c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->connections["\\A"] = RTLIL::SigSpec(w); - c->connections["\\B"] = wr_en; - module->cells[c->name] = c; - - w = new RTLIL::Wire; - w->name = genid(cell->name, "$wren", i, "", j, "$y"); - module->wires[w->name] = w; - c->connections["\\Y"] = RTLIL::SigSpec(w); + RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(j*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(j*mem_width, mem_width); + RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(j*mem_width, mem_width); + RTLIL::Wire *w_seladdr = addr_decode(wr_addr, RTLIL::SigSpec(i, mem_abits)); + + int wr_offset = 0; + while (wr_offset < wr_en.size()) + { + int wr_width = 1; + RTLIL::SigSpec wr_bit = wr_en.extract(wr_offset, 1); + + while (wr_offset + wr_width < wr_en.size()) { + RTLIL::SigSpec next_wr_bit = wr_en.extract(wr_offset + wr_width, 1); + if (next_wr_bit != wr_bit) + break; + wr_width++; + } + + RTLIL::Wire *w = w_seladdr; + + if (wr_bit != RTLIL::SigSpec(1, 1)) + { + RTLIL::Cell *c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and"); + c->parameters["\\A_SIGNED"] = RTLIL::Const(0); + c->parameters["\\B_SIGNED"] = RTLIL::Const(0); + c->parameters["\\A_WIDTH"] = RTLIL::Const(1); + c->parameters["\\B_WIDTH"] = RTLIL::Const(1); + c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); + c->setPort("\\A", w); + c->setPort("\\B", wr_bit); + + w = module->addWire(genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y")); + c->setPort("\\Y", RTLIL::SigSpec(w)); + } + + RTLIL::Cell *c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux"); + c->parameters["\\WIDTH"] = wr_width; + c->setPort("\\A", sig.extract(wr_offset, wr_width)); + c->setPort("\\B", wr_data.extract(wr_offset, wr_width)); + c->setPort("\\S", RTLIL::SigSpec(w)); + + w = module->addWire(genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"), wr_width); + c->setPort("\\Y", w); + + sig.replace(wr_offset, w); + wr_offset += wr_width; + count_wrmux++; + } } - c = new RTLIL::Cell; - c->name = genid(cell->name, "$wrmux", i, "", j); - c->type = "$mux"; - c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - c->connections["\\A"] = sig; - c->connections["\\B"] = wr_data; - c->connections["\\S"] = RTLIL::SigSpec(w); - module->cells[c->name] = c; - - w = new RTLIL::Wire; - w->name = genid(cell->name, "$wrmux", i, "", j, "$y"); - w->width = mem_width; - module->wires[w->name] = w; - c->connections["\\Y"] = RTLIL::SigSpec(w); - sig = RTLIL::SigSpec(w); + module->connect(RTLIL::SigSig(data_reg_in[i], sig)); } - module->connections.push_back(RTLIL::SigSig(data_reg_in[i], sig)); - } - - log(" write interface: %d blocks of $eq, $and and $mux cells.\n", count_wrmux); + log(" write interface: %d write mux blocks.\n", count_wrmux); - module->cells.erase(cell->name); - delete cell; - return; -} + module->remove(cell); + } -static void handle_module(RTLIL::Design *design, RTLIL::Module *module) -{ - std::vector<RTLIL::Cell*> cells; - for (auto &it : module->cells) - if (it.second->type == "$mem" && design->selected(module, it.second)) - cells.push_back(it.second); - for (auto cell : cells) - handle_cell(module, cell); -} + MemoryMapWorker(RTLIL::Design *design, RTLIL::Module *module) : design(design), module(module) + { + std::vector<RTLIL::Cell*> cells; + for (auto cell : module->selected_cells()) + if (cell->type == "$mem" && design->selected(module, cell)) + cells.push_back(cell); + for (auto cell : cells) + handle_cell(cell); + } +}; struct MemoryMapPass : public Pass { MemoryMapPass() : Pass("memory_map", "translate multiport memories to basic cells") { } @@ -348,9 +334,8 @@ struct MemoryMapPass : public Pass { virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { log_header("Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) - if (design->selected(mod_it.second)) - handle_module(design, mod_it.second); + for (auto mod : design->selected_modules()) + MemoryMapWorker(design, mod); } } MemoryMapPass; diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc new file mode 100644 index 000000000..3ae0cd2c7 --- /dev/null +++ b/passes/memory/memory_share.cc @@ -0,0 +1,744 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/satgen.h" +#include "kernel/sigtools.h" +#include "kernel/modtools.h" + +PRIVATE_NAMESPACE_BEGIN + +static bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b) +{ + if (a->type == "$memrd" && b->type == "$memrd") + return a->name < b->name; + if (a->type == "$memrd" || b->type == "$memrd") + return (a->type == "$memrd") < (b->type == "$memrd"); + return a->parameters.at("\\PRIORITY").as_int() < b->parameters.at("\\PRIORITY").as_int(); +} + +struct MemoryShareWorker +{ + RTLIL::Design *design; + RTLIL::Module *module; + SigMap sigmap, sigmap_xmux; + ModWalker modwalker; + CellTypes cone_ct; + + std::map<RTLIL::SigBit, std::pair<RTLIL::Cell*, int>> sig_to_mux; + std::map<std::set<std::map<RTLIL::SigBit, bool>>, RTLIL::SigBit> conditions_logic_cache; + + + // ----------------------------------------------------------------- + // Converting feedbacks to async read ports to proper enable signals + // ----------------------------------------------------------------- + + bool find_data_feedback(const std::set<RTLIL::SigBit> &async_rd_bits, RTLIL::SigBit sig, + std::map<RTLIL::SigBit, bool> &state, std::set<std::map<RTLIL::SigBit, bool>> &conditions) + { + if (async_rd_bits.count(sig)) { + conditions.insert(state); + return true; + } + + if (sig_to_mux.count(sig) == 0) + return false; + + RTLIL::Cell *cell = sig_to_mux.at(sig).first; + int bit_idx = sig_to_mux.at(sig).second; + + std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort("\\A")); + std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort("\\B")); + std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort("\\S")); + std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y")); + log_assert(sig_y.at(bit_idx) == sig); + + for (int i = 0; i < int(sig_s.size()); i++) + if (state.count(sig_s[i]) && state.at(sig_s[i]) == true) { + if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, conditions)) { + RTLIL::SigSpec new_b = cell->getPort("\\B"); + new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); + cell->setPort("\\B", new_b); + } + return false; + } + + + for (int i = 0; i < int(sig_s.size()); i++) + { + if (state.count(sig_s[i]) && state.at(sig_s[i]) == false) + continue; + + std::map<RTLIL::SigBit, bool> new_state = state; + new_state[sig_s[i]] = true; + + if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, conditions)) { + RTLIL::SigSpec new_b = cell->getPort("\\B"); + new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); + cell->setPort("\\B", new_b); + } + } + + std::map<RTLIL::SigBit, bool> new_state = state; + for (int i = 0; i < int(sig_s.size()); i++) + new_state[sig_s[i]] = false; + + if (find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, conditions)) { + RTLIL::SigSpec new_a = cell->getPort("\\A"); + new_a.replace(bit_idx, RTLIL::State::Sx); + cell->setPort("\\A", new_a); + } + + return false; + } + + RTLIL::SigBit conditions_to_logic(std::set<std::map<RTLIL::SigBit, bool>> &conditions, int &created_conditions) + { + if (conditions_logic_cache.count(conditions)) + return conditions_logic_cache.at(conditions); + + RTLIL::SigSpec terms; + for (auto &cond : conditions) { + RTLIL::SigSpec sig1, sig2; + for (auto &it : cond) { + sig1.append_bit(it.first); + sig2.append_bit(it.second ? RTLIL::State::S1 : RTLIL::State::S0); + } + terms.append(module->Ne(NEW_ID, sig1, sig2)); + created_conditions++; + } + + if (terms.size() > 1) + terms = module->ReduceAnd(NEW_ID, terms); + + return conditions_logic_cache[conditions] = terms; + } + + void translate_rd_feedback_to_en(std::string memid, std::vector<RTLIL::Cell*> &rd_ports, std::vector<RTLIL::Cell*> &wr_ports) + { + std::map<RTLIL::SigSpec, std::vector<std::set<RTLIL::SigBit>>> async_rd_bits; + std::map<RTLIL::SigBit, std::set<RTLIL::SigBit>> muxtree_upstream_map; + std::set<RTLIL::SigBit> non_feedback_nets; + + for (auto wire_it : module->wires_) + if (wire_it.second->port_output) { + std::vector<RTLIL::SigBit> bits = RTLIL::SigSpec(wire_it.second); + non_feedback_nets.insert(bits.begin(), bits.end()); + } + + for (auto cell_it : module->cells_) + { + RTLIL::Cell *cell = cell_it.second; + bool ignore_data_port = false; + + if (cell->type == "$mux" || cell->type == "$pmux") + { + std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort("\\A")); + std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort("\\B")); + std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort("\\S")); + std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y")); + + non_feedback_nets.insert(sig_s.begin(), sig_s.end()); + + for (int i = 0; i < int(sig_y.size()); i++) { + muxtree_upstream_map[sig_y[i]].insert(sig_a[i]); + for (int j = 0; j < int(sig_s.size()); j++) + muxtree_upstream_map[sig_y[i]].insert(sig_b[i + j*sig_y.size()]); + } + + continue; + } + + if ((cell->type == "$memwr" || cell->type == "$memrd") && + cell->parameters.at("\\MEMID").decode_string() == memid) + ignore_data_port = true; + + for (auto conn : cell_it.second->connections()) + { + if (ignore_data_port && conn.first == "\\DATA") + continue; + std::vector<RTLIL::SigBit> bits = sigmap(conn.second); + non_feedback_nets.insert(bits.begin(), bits.end()); + } + } + + std::set<RTLIL::SigBit> expand_non_feedback_nets = non_feedback_nets; + while (!expand_non_feedback_nets.empty()) + { + std::set<RTLIL::SigBit> new_expand_non_feedback_nets; + + for (auto &bit : expand_non_feedback_nets) + if (muxtree_upstream_map.count(bit)) + for (auto &new_bit : muxtree_upstream_map.at(bit)) + if (!non_feedback_nets.count(new_bit)) { + non_feedback_nets.insert(new_bit); + new_expand_non_feedback_nets.insert(new_bit); + } + + expand_non_feedback_nets.swap(new_expand_non_feedback_nets); + } + + for (auto cell : rd_ports) + { + if (cell->parameters.at("\\CLK_ENABLE").as_bool()) + continue; + + RTLIL::SigSpec sig_addr = sigmap(cell->getPort("\\ADDR")); + std::vector<RTLIL::SigBit> sig_data = sigmap(cell->getPort("\\DATA")); + + for (int i = 0; i < int(sig_data.size()); i++) + if (non_feedback_nets.count(sig_data[i])) + goto not_pure_feedback_port; + + async_rd_bits[sig_addr].resize(std::max(async_rd_bits.size(), sig_data.size())); + for (int i = 0; i < int(sig_data.size()); i++) + async_rd_bits[sig_addr][i].insert(sig_data[i]); + + not_pure_feedback_port:; + } + + if (async_rd_bits.empty()) + return; + + log("Populating enable bits on write ports of memory %s.%s with aync read feedback:\n", log_id(module), log_id(memid)); + + for (auto cell : wr_ports) + { + RTLIL::SigSpec sig_addr = sigmap_xmux(cell->getPort("\\ADDR")); + if (!async_rd_bits.count(sig_addr)) + continue; + + log(" Analyzing write port %s.\n", log_id(cell)); + + std::vector<RTLIL::SigBit> cell_data = cell->getPort("\\DATA"); + std::vector<RTLIL::SigBit> cell_en = cell->getPort("\\EN"); + + int created_conditions = 0; + for (int i = 0; i < int(cell_data.size()); i++) + if (cell_en[i] != RTLIL::SigBit(RTLIL::State::S0)) + { + std::map<RTLIL::SigBit, bool> state; + std::set<std::map<RTLIL::SigBit, bool>> conditions; + + if (cell_en[i].wire != NULL) { + state[cell_en[i]] = false; + conditions.insert(state); + } + + find_data_feedback(async_rd_bits.at(sig_addr).at(i), cell_data[i], state, conditions); + cell_en[i] = conditions_to_logic(conditions, created_conditions); + } + + if (created_conditions) { + log(" Added enable logic for %d different cases.\n", created_conditions); + cell->setPort("\\EN", cell_en); + } + } + } + + + // ------------------------------------------------------ + // Consolidate write ports that write to the same address + // ------------------------------------------------------ + + RTLIL::SigSpec mask_en_naive(RTLIL::SigSpec do_mask, RTLIL::SigSpec bits, RTLIL::SigSpec mask_bits) + { + // this is the naive version of the function that does not care about grouping the EN bits. + + RTLIL::SigSpec inv_mask_bits = module->Not(NEW_ID, mask_bits); + RTLIL::SigSpec inv_mask_bits_filtered = module->Mux(NEW_ID, RTLIL::SigSpec(RTLIL::State::S1, bits.size()), inv_mask_bits, do_mask); + RTLIL::SigSpec result = module->And(NEW_ID, inv_mask_bits_filtered, bits); + return result; + } + + RTLIL::SigSpec mask_en_grouped(RTLIL::SigSpec do_mask, RTLIL::SigSpec bits, RTLIL::SigSpec mask_bits) + { + // this version of the function preserves the bit grouping in the EN bits. + + std::vector<RTLIL::SigBit> v_bits = bits; + std::vector<RTLIL::SigBit> v_mask_bits = mask_bits; + + std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, std::pair<int, std::vector<int>>> groups; + RTLIL::SigSpec grouped_bits, grouped_mask_bits; + + for (int i = 0; i < bits.size(); i++) { + std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]); + if (groups.count(key) == 0) { + groups[key].first = grouped_bits.size(); + grouped_bits.append_bit(v_bits[i]); + grouped_mask_bits.append_bit(v_mask_bits[i]); + } + groups[key].second.push_back(i); + } + + std::vector<RTLIL::SigBit> grouped_result = mask_en_naive(do_mask, grouped_bits, grouped_mask_bits); + RTLIL::SigSpec result; + + for (int i = 0; i < bits.size(); i++) { + std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]); + result.append_bit(grouped_result.at(groups.at(key).first)); + } + + return result; + } + + void merge_en_data(RTLIL::SigSpec &merged_en, RTLIL::SigSpec &merged_data, RTLIL::SigSpec next_en, RTLIL::SigSpec next_data) + { + std::vector<RTLIL::SigBit> v_old_en = merged_en; + std::vector<RTLIL::SigBit> v_next_en = next_en; + + // The new merged_en signal is just the old merged_en signal and next_en OR'ed together. + // But of course we need to preserve the bit grouping.. + + std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups; + std::vector<RTLIL::SigBit> grouped_old_en, grouped_next_en; + RTLIL::SigSpec new_merged_en; + + for (int i = 0; i < int(v_old_en.size()); i++) { + std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_old_en[i], v_next_en[i]); + if (groups.count(key) == 0) { + groups[key] = grouped_old_en.size(); + grouped_old_en.push_back(key.first); + grouped_next_en.push_back(key.second); + } + } + + std::vector<RTLIL::SigBit> grouped_new_en = module->Or(NEW_ID, grouped_old_en, grouped_next_en); + + for (int i = 0; i < int(v_old_en.size()); i++) { + std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_old_en[i], v_next_en[i]); + new_merged_en.append_bit(grouped_new_en.at(groups.at(key))); + } + + // Create the new merged_data signal. + + RTLIL::SigSpec new_merged_data(RTLIL::State::Sx, merged_data.size()); + + RTLIL::SigSpec old_data_set = module->And(NEW_ID, merged_en, merged_data); + RTLIL::SigSpec old_data_unset = module->And(NEW_ID, merged_en, module->Not(NEW_ID, merged_data)); + + RTLIL::SigSpec new_data_set = module->And(NEW_ID, next_en, next_data); + RTLIL::SigSpec new_data_unset = module->And(NEW_ID, next_en, module->Not(NEW_ID, next_data)); + + new_merged_data = module->Or(NEW_ID, new_merged_data, old_data_set); + new_merged_data = module->And(NEW_ID, new_merged_data, module->Not(NEW_ID, old_data_unset)); + + new_merged_data = module->Or(NEW_ID, new_merged_data, new_data_set); + new_merged_data = module->And(NEW_ID, new_merged_data, module->Not(NEW_ID, new_data_unset)); + + // Update merged_* signals + + merged_en = new_merged_en; + merged_data = new_merged_data; + } + + void consolidate_wr_by_addr(std::string memid, std::vector<RTLIL::Cell*> &wr_ports) + { + if (wr_ports.size() <= 1) + return; + + log("Consolidating write ports of memory %s.%s by address:\n", log_id(module), log_id(memid)); + + std::map<RTLIL::SigSpec, int> last_port_by_addr; + std::vector<std::vector<bool>> active_bits_on_port; + + bool cache_clk_enable = false; + bool cache_clk_polarity = false; + RTLIL::SigSpec cache_clk; + + for (int i = 0; i < int(wr_ports.size()); i++) + { + RTLIL::Cell *cell = wr_ports.at(i); + RTLIL::SigSpec addr = sigmap_xmux(cell->getPort("\\ADDR")); + + if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable || + (cache_clk_enable && (sigmap(cell->getPort("\\CLK")) != cache_clk || + cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity))) + { + cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool(); + cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool(); + cache_clk = sigmap(cell->getPort("\\CLK")); + last_port_by_addr.clear(); + + if (cache_clk_enable) + log(" New clock domain: %s %s\n", cache_clk_polarity ? "posedge" : "negedge", log_signal(cache_clk)); + else + log(" New clock domain: unclocked\n"); + } + + log(" Port %d (%s) has addr %s.\n", i, log_id(cell), log_signal(addr)); + + log(" Active bits: "); + std::vector<RTLIL::SigBit> en_bits = sigmap(cell->getPort("\\EN")); + active_bits_on_port.push_back(std::vector<bool>(en_bits.size())); + for (int k = int(en_bits.size())-1; k >= 0; k--) { + active_bits_on_port[i][k] = en_bits[k].wire != NULL || en_bits[k].data != RTLIL::State::S0; + log("%c", active_bits_on_port[i][k] ? '1' : '0'); + } + log("\n"); + + if (last_port_by_addr.count(addr)) + { + int last_i = last_port_by_addr.at(addr); + log(" Merging port %d into this one.\n", last_i); + + bool found_overlapping_bits = false; + for (int k = 0; k < int(en_bits.size()); k++) { + if (active_bits_on_port[i][k] && active_bits_on_port[last_i][k]) + found_overlapping_bits = true; + active_bits_on_port[i][k] = active_bits_on_port[i][k] || active_bits_on_port[last_i][k]; + } + + // Force this ports addr input to addr directly (skip don't care muxes) + + cell->setPort("\\ADDR", addr); + + // If any of the ports between `last_i' and `i' write to the same address, this + // will have priority over whatever `last_i` wrote. So we need to revisit those + // ports and mask the EN bits accordingly. + + RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->getPort("\\EN")); + + for (int j = last_i+1; j < i; j++) + { + if (wr_ports[j] == NULL) + continue; + + for (int k = 0; k < int(en_bits.size()); k++) + if (active_bits_on_port[i][k] && active_bits_on_port[j][k]) + goto found_overlapping_bits_i_j; + + if (0) { + found_overlapping_bits_i_j: + log(" Creating collosion-detect logic for port %d.\n", j); + RTLIL::SigSpec is_same_addr = module->addWire(NEW_ID); + module->addEq(NEW_ID, addr, wr_ports[j]->getPort("\\ADDR"), is_same_addr); + merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->getPort("\\EN"))); + } + } + + // Then we need to merge the (masked) EN and the DATA signals. + + RTLIL::SigSpec merged_data = wr_ports[last_i]->getPort("\\DATA"); + if (found_overlapping_bits) { + log(" Creating logic for merging DATA and EN ports.\n"); + merge_en_data(merged_en, merged_data, sigmap(cell->getPort("\\EN")), sigmap(cell->getPort("\\DATA"))); + } else { + RTLIL::SigSpec cell_en = sigmap(cell->getPort("\\EN")); + RTLIL::SigSpec cell_data = sigmap(cell->getPort("\\DATA")); + for (int k = 0; k < int(en_bits.size()); k++) + if (!active_bits_on_port[last_i][k]) { + merged_en.replace(k, cell_en.extract(k, 1)); + merged_data.replace(k, cell_data.extract(k, 1)); + } + } + + // Connect the new EN and DATA signals and remove the old write port. + + cell->setPort("\\EN", merged_en); + cell->setPort("\\DATA", merged_data); + + module->remove(wr_ports[last_i]); + wr_ports[last_i] = NULL; + + log(" Active bits: "); + std::vector<RTLIL::SigBit> en_bits = sigmap(cell->getPort("\\EN")); + active_bits_on_port.push_back(std::vector<bool>(en_bits.size())); + for (int k = int(en_bits.size())-1; k >= 0; k--) + log("%c", active_bits_on_port[i][k] ? '1' : '0'); + log("\n"); + } + + last_port_by_addr[addr] = i; + } + + // Clean up `wr_ports': remove all NULL entries + + std::vector<RTLIL::Cell*> wr_ports_with_nulls; + wr_ports_with_nulls.swap(wr_ports); + + for (auto cell : wr_ports_with_nulls) + if (cell != NULL) + wr_ports.push_back(cell); + } + + + // -------------------------------------------------------- + // Consolidate write ports using sat-based resource sharing + // -------------------------------------------------------- + + void consolidate_wr_using_sat(std::string memid, std::vector<RTLIL::Cell*> &wr_ports) + { + if (wr_ports.size() <= 1) + return; + + ezDefaultSAT ez; + SatGen satgen(&ez, &modwalker.sigmap); + + // find list of considered ports and port pairs + + std::set<int> considered_ports; + std::set<int> considered_port_pairs; + + for (int i = 0; i < int(wr_ports.size()); i++) { + std::vector<RTLIL::SigBit> bits = modwalker.sigmap(wr_ports[i]->getPort("\\EN")); + for (auto bit : bits) + if (bit == RTLIL::State::S1) + goto port_is_always_active; + if (modwalker.has_drivers(bits)) + considered_ports.insert(i); + port_is_always_active:; + } + + log("Consolidating write ports of memory %s.%s using sat-based resource sharing:\n", log_id(module), log_id(memid)); + + bool cache_clk_enable = false; + bool cache_clk_polarity = false; + RTLIL::SigSpec cache_clk; + + for (int i = 0; i < int(wr_ports.size()); i++) + { + RTLIL::Cell *cell = wr_ports.at(i); + + if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable || + (cache_clk_enable && (sigmap(cell->getPort("\\CLK")) != cache_clk || + cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity))) + { + cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool(); + cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool(); + cache_clk = sigmap(cell->getPort("\\CLK")); + } + else if (i > 0 && considered_ports.count(i-1) && considered_ports.count(i)) + considered_port_pairs.insert(i); + + if (cache_clk_enable) + log(" Port %d (%s) on %s %s: %s\n", i, log_id(cell), + cache_clk_polarity ? "posedge" : "negedge", log_signal(cache_clk), + considered_ports.count(i) ? "considered" : "not considered"); + else + log(" Port %d (%s) unclocked: %s\n", i, log_id(cell), + considered_ports.count(i) ? "considered" : "not considered"); + } + + if (considered_port_pairs.size() < 1) { + log(" No two subsequent ports in same clock domain considered -> nothing to consolidate.\n"); + return; + } + + // create SAT representation of common input cone of all considered EN signals + + std::set<RTLIL::Cell*> sat_cells; + std::set<RTLIL::SigBit> bits_queue; + std::map<int, int> port_to_sat_variable; + + for (int i = 0; i < int(wr_ports.size()); i++) + if (considered_port_pairs.count(i) || considered_port_pairs.count(i+1)) + { + RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->getPort("\\EN")); + port_to_sat_variable[i] = ez.expression(ez.OpOr, satgen.importSigSpec(sig)); + + std::vector<RTLIL::SigBit> bits = sig; + bits_queue.insert(bits.begin(), bits.end()); + } + + while (!bits_queue.empty()) + { + std::set<ModWalker::PortBit> portbits; + modwalker.get_drivers(portbits, bits_queue); + bits_queue.clear(); + + for (auto &pbit : portbits) + if (sat_cells.count(pbit.cell) == 0 && cone_ct.cell_known(pbit.cell->type)) { + std::set<RTLIL::SigBit> &cell_inputs = modwalker.cell_inputs[pbit.cell]; + bits_queue.insert(cell_inputs.begin(), cell_inputs.end()); + sat_cells.insert(pbit.cell); + } + } + + log(" Common input cone for all EN signals: %d cells.\n", int(sat_cells.size())); + + for (auto cell : sat_cells) + satgen.importCell(cell); + + log(" Size of unconstrained SAT problem: %d variables, %d clauses\n", ez.numCnfVariables(), ez.numCnfClauses()); + + // merge subsequent ports if possible + + for (int i = 0; i < int(wr_ports.size()); i++) + { + if (!considered_port_pairs.count(i)) + continue; + + if (ez.solve(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i))) { + log(" According to SAT solver sharing of port %d with port %d is not possible.\n", i-1, i); + continue; + } + + log(" Merging port %d into port %d.\n", i-1, i); + port_to_sat_variable.at(i) = ez.OR(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i)); + + RTLIL::SigSpec last_addr = wr_ports[i-1]->getPort("\\ADDR"); + RTLIL::SigSpec last_data = wr_ports[i-1]->getPort("\\DATA"); + std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(wr_ports[i-1]->getPort("\\EN")); + + RTLIL::SigSpec this_addr = wr_ports[i]->getPort("\\ADDR"); + RTLIL::SigSpec this_data = wr_ports[i]->getPort("\\DATA"); + std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(wr_ports[i]->getPort("\\EN")); + + RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en); + + wr_ports[i]->setPort("\\ADDR", module->Mux(NEW_ID, last_addr, this_addr, this_en_active)); + wr_ports[i]->setPort("\\DATA", module->Mux(NEW_ID, last_data, this_data, this_en_active)); + + std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en; + RTLIL::SigSpec grouped_last_en, grouped_this_en, en; + RTLIL::Wire *grouped_en = module->addWire(NEW_ID, 0); + + for (int j = 0; j < int(this_en.size()); j++) { + std::pair<RTLIL::SigBit, RTLIL::SigBit> key(last_en[j], this_en[j]); + if (!groups_en.count(key)) { + grouped_last_en.append_bit(last_en[j]); + grouped_this_en.append_bit(this_en[j]); + groups_en[key] = grouped_en->width; + grouped_en->width++; + } + en.append(RTLIL::SigSpec(grouped_en, groups_en[key])); + } + + module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en); + wr_ports[i]->setPort("\\EN", en); + + module->remove(wr_ports[i-1]); + wr_ports[i-1] = NULL; + } + + // Clean up `wr_ports': remove all NULL entries + + std::vector<RTLIL::Cell*> wr_ports_with_nulls; + wr_ports_with_nulls.swap(wr_ports); + + for (auto cell : wr_ports_with_nulls) + if (cell != NULL) + wr_ports.push_back(cell); + } + + + // ------------- + // Setup and run + // ------------- + + MemoryShareWorker(RTLIL::Design *design, RTLIL::Module *module) : + design(design), module(module), sigmap(module) + { + std::map<std::string, std::pair<std::vector<RTLIL::Cell*>, std::vector<RTLIL::Cell*>>> memindex; + + sigmap_xmux = sigmap; + for (auto &it : module->cells_) + { + RTLIL::Cell *cell = it.second; + + if (cell->type == "$memrd") + memindex[cell->parameters.at("\\MEMID").decode_string()].first.push_back(cell); + + if (cell->type == "$memwr") + memindex[cell->parameters.at("\\MEMID").decode_string()].second.push_back(cell); + + if (cell->type == "$mux") + { + RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort("\\A")); + RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort("\\B")); + + if (sig_a.is_fully_undef()) + sigmap_xmux.add(cell->getPort("\\Y"), sig_b); + else if (sig_b.is_fully_undef()) + sigmap_xmux.add(cell->getPort("\\Y"), sig_a); + } + + if (cell->type == "$mux" || cell->type == "$pmux") + { + std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y")); + for (int i = 0; i < int(sig_y.size()); i++) + sig_to_mux[sig_y[i]] = std::pair<RTLIL::Cell*, int>(cell, i); + } + } + + for (auto &it : memindex) { + std::sort(it.second.first.begin(), it.second.first.end(), memcells_cmp); + std::sort(it.second.second.begin(), it.second.second.end(), memcells_cmp); + translate_rd_feedback_to_en(it.first, it.second.first, it.second.second); + consolidate_wr_by_addr(it.first, it.second.second); + } + + cone_ct.setup_internals(); + cone_ct.cell_types.erase("$mul"); + cone_ct.cell_types.erase("$mod"); + cone_ct.cell_types.erase("$div"); + cone_ct.cell_types.erase("$pow"); + cone_ct.cell_types.erase("$shl"); + cone_ct.cell_types.erase("$shr"); + cone_ct.cell_types.erase("$sshl"); + cone_ct.cell_types.erase("$sshr"); + cone_ct.cell_types.erase("$shift"); + cone_ct.cell_types.erase("$shiftx"); + + modwalker.setup(design, module, &cone_ct); + + for (auto &it : memindex) + consolidate_wr_using_sat(it.first, it.second.second); + } +}; + +struct MemorySharePass : public Pass { + MemorySharePass() : Pass("memory_share", "consolidate memory ports") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" memory_share [selection]\n"); + log("\n"); + log("This pass merges share-able memory ports into single memory ports.\n"); + log("\n"); + log("The following methods are used to consolidate the number of memory ports:\n"); + log("\n"); + log(" - When write ports are connected to async read ports accessing the same\n"); + log(" address, then this feedback path is converted to a write port with\n"); + log(" byte/part enable signals.\n"); + log("\n"); + log(" - When multiple write ports access the same address then this is converted\n"); + log(" to a single write port with a more complex data and/or enable logic path.\n"); + log("\n"); + log(" - When multiple write ports are never accessed at the same time (a SAT\n"); + log(" solver is used to determine this), then the ports are merged into a single\n"); + log(" write port.\n"); + log("\n"); + log("Note that in addition to the algorithms implemented in this pass, the $memrd\n"); + log("and $memwr cells are also subject to generic resource sharing passes (and other\n"); + log("optimizations) such as opt_share.\n"); + log("\n"); + } + virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { + log_header("Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n"); + extra_args(args, 1, design); + for (auto module : design->selected_modules()) + MemoryShareWorker(design, module); + } +} MemorySharePass; + +PRIVATE_NAMESPACE_END + diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index 782c0cd79..5a4c4eac9 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -22,7 +22,6 @@ #include <sstream> #include <algorithm> #include <stdlib.h> -#include <assert.h> static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) { @@ -32,7 +31,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) RTLIL::IdString mem_name = RTLIL::escape_id(memory->parameters.at("\\MEMID").decode_string()); while (module->memories.count(mem_name) != 0) - mem_name += stringf("_%d", RTLIL::autoidx++); + mem_name = mem_name.str() + stringf("_%d", autoidx++); RTLIL::Memory *mem = new RTLIL::Memory; mem->name = mem_name; @@ -47,51 +46,44 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) for (int i = 0; i < num_rd_ports; i++) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - cell->type = "$memrd"; - cell->parameters["\\MEMID"] = mem_name; + RTLIL::Cell *cell = module->addCell(NEW_ID, "$memrd"); + cell->parameters["\\MEMID"] = mem_name.str(); cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS"); cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH"); cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const(); cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_POLARITY")).extract(i, 1).as_const(); cell->parameters["\\TRANSPARENT"] = RTLIL::SigSpec(memory->parameters.at("\\RD_TRANSPARENT")).extract(i, 1).as_const(); - cell->connections["\\CLK"] = memory->connections.at("\\RD_CLK").extract(i, 1); - cell->connections["\\ADDR"] = memory->connections.at("\\RD_ADDR").extract(i*abits, abits); - cell->connections["\\DATA"] = memory->connections.at("\\RD_DATA").extract(i*mem->width, mem->width); - module->add(cell); + cell->setPort("\\CLK", memory->getPort("\\RD_CLK").extract(i, 1)); + cell->setPort("\\ADDR", memory->getPort("\\RD_ADDR").extract(i*abits, abits)); + cell->setPort("\\DATA", memory->getPort("\\RD_DATA").extract(i*mem->width, mem->width)); } for (int i = 0; i < num_wr_ports; i++) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - cell->type = "$memwr"; - cell->parameters["\\MEMID"] = mem_name; + RTLIL::Cell *cell = module->addCell(NEW_ID, "$memwr"); + cell->parameters["\\MEMID"] = mem_name.str(); cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS"); cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH"); cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const(); cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_POLARITY")).extract(i, 1).as_const(); cell->parameters["\\PRIORITY"] = i; - cell->connections["\\CLK"] = memory->connections.at("\\WR_CLK").extract(i, 1); - cell->connections["\\EN"] = memory->connections.at("\\WR_EN").extract(i, 1); - cell->connections["\\ADDR"] = memory->connections.at("\\WR_ADDR").extract(i*abits, abits); - cell->connections["\\DATA"] = memory->connections.at("\\WR_DATA").extract(i*mem->width, mem->width); - module->add(cell); + cell->setPort("\\CLK", memory->getPort("\\WR_CLK").extract(i, 1)); + cell->setPort("\\EN", memory->getPort("\\WR_EN").extract(i*mem->width, mem->width)); + cell->setPort("\\ADDR", memory->getPort("\\WR_ADDR").extract(i*abits, abits)); + cell->setPort("\\DATA", memory->getPort("\\WR_DATA").extract(i*mem->width, mem->width)); } - module->cells.erase(memory->name); - delete memory; + module->remove(memory); } static void handle_module(RTLIL::Design *design, RTLIL::Module *module) { std::vector<RTLIL::IdString> memcells; - for (auto &cell_it : module->cells) + for (auto &cell_it : module->cells_) if (cell_it.second->type == "$mem" && design->selected(module, cell_it.second)) memcells.push_back(cell_it.first); for (auto &it : memcells) - handle_memory(module, module->cells.at(it)); + handle_memory(module, module->cells_.at(it)); } struct MemoryUnpackPass : public Pass { @@ -109,7 +101,7 @@ struct MemoryUnpackPass : public Pass { virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { log_header("Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) handle_module(design, mod_it.second); } |