diff options
Diffstat (limited to 'passes/hierarchy/hierarchy.cc')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index a2a428d15..225e1feae 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -224,7 +224,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check { {".v", "verilog"}, {".sv", "verilog -sv"}, - {".il", "ilang"} + {".il", "rtlil"} }; for (auto &ext : extensions_list) @@ -765,11 +765,13 @@ struct HierarchyPass : public Pass { top_mod = design->module(top_name); dict<RTLIL::IdString, RTLIL::Const> top_parameters; - for (auto ¶ : parameters) { - SigSpec sig_value; - if (!RTLIL::SigSpec::parse(sig_value, NULL, para.second)) - log_cmd_error("Can't decode value '%s'!\n", para.second.c_str()); - top_parameters[RTLIL::escape_id(para.first)] = sig_value.as_const(); + if ((top_mod == nullptr && design->module(abstract_id)) || top_mod != nullptr) { + for (auto ¶ : parameters) { + SigSpec sig_value; + if (!RTLIL::SigSpec::parse(sig_value, NULL, para.second)) + log_cmd_error("Can't decode value '%s'!\n", para.second.c_str()); + top_parameters[RTLIL::escape_id(para.first)] = sig_value.as_const(); + } } if (top_mod == nullptr && design->module(abstract_id)) |